微處理器自我測試程式的故障模擬技術

A Test Program Fault Simulator for Microprocessor Software-Based Self-Testing

吳佳龍(Jiang Jung Wu)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.02622

摘要

中文摘要
對於極複雜的系統單晶片測試技術來說， 使用增加硬體電路測試(Built-In Self-Test, BIST or scan chain insertion)，雖然可以得到較高的故障涵蓋( fault coverage)，但同時會產生高功率消耗以及電路面積增加的問題。為了解決上述兩項缺點，以微處理器核心指令集為基礎，針對嵌入式處理器的軟體自我測試方式近年來已經成為另外一種測試的主流方式。軟體自我測試方式是利用微處理器本身提供的指令集，以及自行撰寫的組合語言(assembly codes)，建立成一組一組的測試程式(test program candidates)。使用者可使用這些測試程式針對電路做偵錯的動作，同時記錄每一個時序週期(clock cycle)產生的信號，這些信號可稱之為測試信號(test vectors)。將得到的測試信號轉成標準的測試語言程式(Standard Test Interface Language, STIL)，測試語言程式經由故障模擬器（fault simulator）與電路檔案一起做模擬，可得到故障涵蓋、故障辭典(fault dictionary)。
本研究提出一個高準確性的自動化故障模擬器(Automatic Fault Simulator)用以計算使用者所提供的測試程式。使用者可根據故障涵蓋以及故障辭典的結果，修改或是組合出更好的測試程式以提高測試程式的故障涵蓋，進而媲美使用增加硬體電路的方式；同時我們發展出一套流程去確認故障模擬技術是否符合原來所給予的測試程式而沒有更動原來的功能。
最後利用Parwan微處理器和8051微控制器作為測試範例、驗證我們所提出的方法，並且比較其結果。

關鍵字

故障模擬器 ； 測試程式 ； 內建自我測試電路 ； 故障字典 ； 故障涵蓋

並列摘要

Abstract
Software self-testing for embedded processor cores based on their instruction sets is a topic of increasing interest. Since it provides an excellent test resource partitioning technique for sharing the testing task of complex System-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. Although BIST or scan chain can provide higher fault coverage for complex SoC, higher power consumption and area overhead are two issues that should be solved. Software self-testing concept is to utilize the instruction sets provided by microprocessors or microcontrollers. The users can establish test program candidates by combining the instructions. Users can perform logic simulation and detect structural faults with test program candidates, record the signals in every clock cycle at the same time. The signals which were recorded in every clock cycle are called test vectors.
The purpose of proposed fault simulator is to transfer test vectors into test file like STIL (standard test interface language) which can be accepted by fault simulator, and evaluate fault coverage, fault dictionary with circuit files.
In the thesis, we present a high accuracy fault simulator for user defined test program candidates to evaluate fault coverage by performing fault simulation without modifying the original design. We acquire some useful information like fault coverage, fault dictionary through fault simulation. Users can compare the quality of these test program candidates and find out which candidate can detect the most faults. In addition, higher fault coverage could be achieved by combining test program candidates or finding some specific ordering. Some experiments are established to validate the proposed fault simulator.
The Parwan and 8051 IP cores are taken for experiments. Some test programs come from public literature and others are from public websites. Before performing fault simulation, the correctness of function was validated in the beginning. Simulation results are shown to validate the proposed technique.

並列關鍵字

Fault dictionary ； test program ； fault simulator ； Fault coverage ； Built-in-Self-Test

參考文獻

[1] V.D.Agrawal et al., “BIST for digital Integrated Circuits”, AT&T Tech. Journal, March 1994, pp30.

[2] J.Shen, J.Abraham, “Native mode functional test generation for processors with applications to self-test and design validation”, ITC 1998, pp. 990-999.

[3] K.Batcher, C.Papachristou, “Instruction randomization self test for processor cores”, VTS 1999, pp. 34 – 40.

[4] K.Radecka, J.Rajski, J. Tyszer, “Arithmetic built-in selftest for DSP cores,” IEEE Trans. on CAD, vol.16, no.11, Nov. 1997, pp. 1358–1369.

[6] S.Hellebrand, H.-J.Wunderlich, “Mixed-mode BIST using embedded processors”, ITC 1996, pp. 195 – 204.