不均勻結構金氧半穿隧二極體之雙態特性與暫態行為

Two-State Characteristics and Transient Behavior in Metal-Insulator-Semiconductor Tunnel Diode with Structural Non-Uniformity

林家德(Chia-Te Lin)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201801189

摘要

本篇論文中，我們藉由調整傳統金氧半穿隧二極體的結構使元件的暫態反應及雙態現象獲得提升。在論文的第二章中我們透過製備邊緣延伸性閘極薄金屬的金氧半穿隧二極體結構讓邊緣的延伸性薄金屬在偏壓下呈現電阻特性，使得載子在來回掃動的電容-電壓量測中的暫態反應增加而展現明顯的雙態電容特性和電容遲滯現象。而為了測試這個元件的電容雙態特性是否夠穩定來作為傳統隨機存取記憶體之應用，我們對此元件進行了基本的耐久性測試，並且對於此元件在脈衝操作下的反應機制進行了更深入的研究。在論文的第三章中，透過調變傳統金氧半穿隧二極體在邊緣絕緣層的氧化層厚度來產生結構的不均勻性。由於氧化層厚度的差異，使得元件在電流-電壓量測中會產生額外的暫態電流而造成來回掃動的電流差異，並顯現出明顯的雙態電流特性。此外，我們也發現此元件的雙態特性會與量測的速率和掃動的範圍有關。

關鍵字

MIS Tunnel diode ； memory ； two-state characteristics ； structural non-uniformity

並列摘要

In this thesis, transient response and two-state characteristics of our targeting devices have definitely gotten enhanced through some simple adjustment to the well-investigated conventional MIS structure. In chapter 2, by thinning the edging part of gate metal for traditional MIS to reveal the resistance-like property, carriers’ transient response has been enlarged through forward and reverse C-V measurements, displaying distinguishable two-state capacitance and increasing C-V hysteresis through voltage sweeping. Furthermore, endurance characteristic is also demonstrated to test the capability of being a future alternative of memory applications. Also, detailed mechanism under bias condition is then discussed on both structures. In chapter 3, in another way, we fabricate MIS devices with uneven oxide (UEOMIS) at the edge to create structural non-uniformity. Through the variation of current conduction between bulk and edge, transient phenomenon is then discovered during I-V measurements, exhibiting obvious two-state characteristic of current. Moreover, further investigation has been practiced to show that the transient phenomenon in UEOMIS devices is closely related to the sweeping rate and sweeping range. Last but not least, endurance and retention characteristics are also applied to check out the reliability of our devices.

並列關鍵字

金氧半穿隧二極體 ； 記憶體 ； 雙態特性 ； 不均勻結構

參考文獻

[1] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, "An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications," in IEEE Journal of Solid-State Circuits.

[2] R. Giterman, A. Fish, A. Burg and A. Teman, "A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 4, pp. 1245-1256, April 2018.

[3] E. Yoshida and T. Tanaka, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory," in IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 692-697, April 2006.

[4] N. Rodriguez, S. Cristoloveanu and F. Gamiz, "Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates," in IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2371-2377, Aug. 2011.

[5] Y. D. Tan and J. G. Hwu, “2-State Current Characteristics of MOSCAP with Ultrathin Oxide and Metal Gate,” ECS Solid State Lett., vol. 4, no. 12, pp. N23-N25, Nov. 2015.