用於測試訊號產生的三角積分調變器位元流之最佳化與壓縮技術

Optimization and Compression for Sigma–Delta Modulation Based Signal Generation

林耕平(Geng-Ping Lin)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.03009

摘要

在許多的研究及報告中，類比測試訊號可以使用一個由三角積分器產生的位元流透過低通濾波器來產生，然而，在自我內建測試的應用上，其用來儲存位元流的記憶體是有限的，而這可能會大幅限制了所能夠產生的類比測試訊號品質。在這篇論文裡，首先，我們確認由我們產生的高品質位元流的確符合測試訊號規格。 接著，我們以軟體實做出用來壓縮位元流的編碼器，以及相對應用來解壓縮的硬體解碼器。由硬體解碼器所解壓縮出來的位元流，將被用來產生類比訊號。

關鍵字

三角積分器調變器 ； 位元流最佳化 ； 壓縮

並列摘要

It has been reported that analog test stimulus generation may be realized by low pass filtering a sigma-delta modulated 1-bit data stream. However, for BIST (Built-In Self-Test) applications, the available storage for storing the bit steam may limit the quality of the generated analog signal. In this thesis, we first identify a high-quality bit stream that meets the test signal specification. Then we implement the software encoder to compress the bit stream, and the corresponding hardware decoder (to be implemented on-chip) to decompress the bit stream for analog signal generation.

並列關鍵字

sigma-delta modulator ； bitstream optimization ； compression

參考文獻

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[8] B. Dufort and G. W. Roberts, “Signal generation using periodic single and multi bit Sigma-Delta modulated streams,” IEEE International Test Conference, pp. 396–405, Nov. 1997.

[9] B. Dufort and G. W. Roberts, “Optimized periodic Sigma-Delta bitstream for analog signal generation,” IEEE Midwest Symposium on Circuits and Systems,