運用於有線傳送接收機之CMOS時脈產生及時脈資料回復電路的設計與實現

Design and Implementation of CMOS Clock Generation and Clock/Data Recovery Circuits for Wired-line Transceivers

楊榮吉(Rong-Jyi Yang)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2006年)

https://doi.org/10.6342/NTU.2006.10511

摘要

隨著CMOS製程的進步﹐有越來越多的數位電路整合到一顆的IC之中﹐因此現今的商品可以提供許多的有方便介面的功能給使用者﹐讓使用者可以輕易地將數位化的多媒體訊息傳送到個人電腦或是個人數位助理上﹐並經由網際網路與朋友分享﹐因此﹐在給手持式裝置所使用的有線傳輸介面﹐以及光纖網路的需求逐漸增加。隨著有線通訊系統資料速率的提升﹐電路操作的時間安全範圍漸漸變短﹐而時脈的相位誤差和抖動將使得操作這些數位電路變得更困難﹐所以在時脈產生及時脈資料回復電路設計上的挑戰也更加提高。
延遲鎖定迴路廣泛地運用在時脈同步的問題上﹐因為與傳統的鎖相迴路相比﹐它無條件穩定、有較快的暫態反應﹐同時有較少的抖動累積的現象。然而﹐它主要的缺點就是操作的頻率範圍較窄﹐同時沒有電源雜訊壓制的特性。在另一方面﹐時脈資料回復電路在通訊系統的接收端扮演著重要的角色﹐不使用參考訊號的架構﹐與傳統的以鎖相迴路為基礎的時脈資料回復電路相比﹐因為沒有參考訊號與資料速率之間存在頻率誤差的問題﹐似乎是比較好的選擇﹐不過﹐由於那種架構需要一個可大範圍操作的頻率偵測器﹐變成整個時脈資料回復電路設計上的瓶頸。本論文的主軸就是要克服這些缺點﹐打破傳統限制﹐並為延遲鎖定迴路以及時脈資料回復電路提供一個具有彈性的應用方式。
在本論文中首先介紹的是使用數位方式輔助的延遲鎖定迴路及時脈資料回復電路﹐利用數位方式來延伸操作的頻率範圍﹐降低類比操作中壓控震盪器/壓控延遲線的轉換增益﹐使得在大範圍的操作頻率下依然能保持傳統類比方式的低抖動的特性。接著呈現的是使用數位方式實現的延遲鎖定迴路及時脈資料回復電路﹐利用我所提出的可變長度之二元搜尋演算法﹐全數位的延遲鎖定迴路可以在大範圍的操作頻率下都使用二元搜尋法來減少鎖定時間﹐而不會有諧波鎖定的問題﹐再者﹐利用我所提出的平衡式時脈緣結合電路以及晶格式延遲單元﹐此延遲鎖定迴路可以輸出同步及百分之五十責任週期的時脈﹐不需使用互補式時脈的方式或是雙迴路的架構。再者﹐利用我所提出的隨機訊號之相位頻率偵測器﹐數位式的時脈資料回復電路可以做二元的頻率追蹤以及快速的相位鎖定。另外﹐本論文亦提供數種延遲鎖定迴路及時脈資料回復電路的理論分析來驗證電路實現的結果。

關鍵字

時脈產生器 ； 延遲鎖定迴路 ； 時脈資料回復電路 ； 頻率偵測器

並列摘要

With the progress of the CMOS technologies, more and more digital circuits are integrated in a monolithic IC. Thus the commercial products can provide many useful functions with friendly user interfaces for the customers. The digitized multi-media information can be transferred into personal computers or personal digital assistant and shared with friends via the Internet. Thus the demands of the high-speed wired-line interfaces for the handheld devices and the optical communication network for the Internet grow gradually. As the increase of the baud rate for the wired-line communications, the timing margin for the wired-line transceivers is shrinking. Hence the challenge for the clock generation and clock/data recovery circuits also advances.
Delay-locked loops (DLLs) are widely used to solve the issue of clock synchronization due to its un-conditionally stable, faster transient response and less jitter accumulation than the phase-locked loops (PLLs). However, the narrow operating frequency range and no supply noise suppression become the major drawbacks for the DLLs. On the other hand, the clock/data recovery (CDR) circuits play an important pole in the receiver end of the communication systems. The reference-less configuration is better choice than the conventional PLL-based CDR because there is no frequency offset issue between the reference frequency and the input data rate. Nevertheless, the demand for a frequency detector with a wide range of bit rate becomes the bottleneck in the CDR design. Thus the subject of this dissertation is to overcome the defects, to break the limitations and to make a flexible use for the conventional DLLs and the CDR circuits.
The digitally assisted DLL and CDR circuit are introduced first to extend the operating frequency range and lower the conversion gain of the voltage-controlled oscillator / voltage-controlled delay line for the analog operation. The low jitter characteristic of the conventional analog approach is also maintained for the wide range operation. The digitally implemented DLL and CDR circuit are presented then. With the aid of the proposed variable successive approximation register-controlled algorithm, the all-digital DLL can perform the binary search over a wide frequency range without the harmonic locking issue. With the aid of the proposed balanced edge combiner and the lattice delay unit, the DLL outputs a synchronous clock with 50% duty cycle with neither the complementary clocks nor the dual loops architecture. Further, with the aid of the proposed binary phase/frequency detector for the random NRZ data, the digital CDR circuit can perform a binary frequency acquisition and a fast phase tracking. Moreover, several theoretical analyses for the DLLs and CDR circuit are also given to be consistent with the circuit realizations in the dissertation.

並列關鍵字

clock generator ； DLL ； CDR ； PLL ； frequency detector ； quadricorrelator

參考文獻

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