以熱為導向的連線最佳化

THERMAL-DRIVEN INTERCONNECT OPTIMIZATION BY SIMULTANEOUS GATE AND WIRE SIZING

林宜偉(Yi-Wei Lin)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.02308

摘要

隨著能量消耗和電路密度的急劇增加，導致晶片操作溫度的升高，影響晶片可靠度以及效能，所以溫度、電子遷移、面積、時序與能量都是奈米時代積體電路設計的重要考量。在本論文中，我們模擬了溫度對連線時序延遲與電子遷移可靠度的影響，並利用最小平方差法，得到 posynomial 方程式去趨近連線溫度，我們依據 Lagrangian relaxation，提出改變電路元件的大小的演算法，此演算法能夠同時處理連線溫度、電子遷移、面積、時序與能量的最佳化。實驗結果顯示，原來 11.56% 不會通過電子遷移可靠度要求的連線，經過我們所提出的演算法能夠找到使得全部連線滿足電子遷移可靠度要求的解，而且平均而言，在面積、最大溫度增加、時序與能量消耗分別有11.84%、10.96%、70.75% 和 12.01% 的進步。

關鍵字

連線最佳化 ； 熱效應

並列摘要

The dramatic increase of power consumption and integration density has led
to high operating temperature. Temperature, as well as electromigration (EM), area,
timing, and power, has become one of the most important concerns in the design
of nanometer integrated circuits. In this thesis, we model the effects of thermal
on both interconnect delay and EM reliability. Applying the least square estimator
(LSE) method, we develop a posynomial formula to approximate interconnect
temperature and present an algorithm that can optimally solve the simultaneous interconnect
temperature, EM, area, delay, and power optimization problem by sizing
circuit components based on Lagrangian relaxation. The experimental results show
that our algorithm can find desired solutions that satisfy all EM reliability requirements
from 11.56% failures among all wires initially. On the average, it improves the
respective area, maximal temperature increase, delay, and power by 11.84%, 10.96%,
70.75%, and 12.01% after wire and gate sizing.

並列關鍵字

interconnect optimization ； thermal effects

參考文獻

pp. 44-48, Nov. 2001.

Jun. 1999.

237, Apr. 2001.

Hajj, “Post-Route Gate Sizing for Crosstalk Noise Reduction,” in Proc. Design

[5] A. A. Bilotti, “Static Temperature Distribution in IC Chips with Isothermal Heat