應用於晶片間的12Gb/s電容耦合傳送接收器

隨著多媒體科技的發展，高速I/O成為各種電路中不可或缺的一部分。雖然時脈可操作於很高的頻率，但傳送接收器卻無法達到相對的速度。再者由於手提電子的需求，低功率考量也成為重要的一個環節。因此如何設計出高速低功率的傳送接收器成為現今重要的議題。本篇論文描述了一個高速且低功率損耗電容耦合傳送接收器。這種電容耦合式傳送接收器可將NRZ的資料轉換成低振幅的脈衝波，經由傳輸線傳送後，於接收端再將此脈衝波還原成NRZ的資料。在傳送端使用互補式傳輸線為基礎的鎖相迴路來提供時脈，並使用差動的傳送器來降低雜訊。而接收端電路使用被動但低功率損耗的等化器來彌補高頻的損失，以及使用電流模式的Sense Amplifier將脈衝波回復成NRZ的資料，最後利用改良的Cherry-Hooper放大器將波形放大。此低擺幅的脈衝波傳送接收器，可以使用被動的等化器來降低功率損耗，而電流模式的Sense Amplifier則可以達到高速的應用，並且可利用耦合電容大小的選取，有效的降低ISI。最後實際以TSMC CMOS 0.18um製程下線，使用2^15-1的PRBS來給資料，將資料透過75fF電容經由10公分的FR4傳輸線來傳輸，最大可到達12Gb/s的傳輸速度。傳送器與接收器消耗的功率分別為21.3mW和13.5mW，而誤碼率小於10-12，整個晶片的面積則為500x735um2和250x350um2。

關鍵字

電容耦合介面；傳送接收器；低擺幅脈衝波；互補式傳輸線；鎖相迴路

並列摘要

Transceiver is the critical circuit in many systems. With the growing of the media technology, high speed I/O is indispensable for many applications. Moreover, for the portable applications, low power consumption is also an important issue. Thus how to design a high speed and low power I/O is the main propose of this thesis. This thesis describes a low-power and high-speed AC coupled transceiver architecture for high density interconnects. This transmitter can convert non-return to zero (NRZ) data into return to zero (RZ) pulse, then sending pulse through transmission line, and recovering pulse to NRZ data at receiver. At the transmitter side, we use phase-locked loop with complementary transmission line to be clock signals. At the receiver side, sense amplifier is used to recover NRZ data from pulse. Using this low swing pulse transceiver, 12Gb/s chip-to-chip communication is demonstrated through a wire-bonded AC coupled interconnect (ACCI) channel with 75-fF coupling capacitors, across 10-cm FR4 micro-strip lines. A test chip was fabricated in TSMC 0.18-um CMOS technology, and for 2^15-1 PRBS at 12Gb/s, transmitter and receiver circuits consumed 21.3mW and 13.5mW respectively with a bit error rate less than 10^-12 . It occupies an active area of 500x735um2 and 250x350um2.

並列關鍵字

AC coupled interconnect (ACCI) ； PLL ； transceiver ； low swing pulse

參考文獻

[1] Lue L.; Wilson, J.M.; Mick, S.E.; Jian Xu; Liang Zhang; Franzon, P.D.; “3Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver”, IEEE J. Solid-State Circuits, VOL. 41, NO. 1, 2006

[2] Gabara, T.J.; Fischer, W.C.; “Capacitive coupling and quantized feedback applied to conventional CMOS technology,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 419–427, Mar. 1997.

[3] J. Kim, I. Verbauwhede, and M.-C. F. Chang, “A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1331–1340, Jun. 2005.

[4] S. E. Mick, J. M. Wilson, and P. D. Franzon, “4 Gbps high-density AC coupled interconnection,” in Proc. IEEE Custom Integrate. Circuits Conf., May 2002, pp. 133–140.

[5] S. A. Kühn, M. B. Kleiner, R. Thewes, and W. Weber, “Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling,”in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, Apr. 1995, pp.37–40.

國際替代計量

應用於晶片間的12Gb/s電容耦合傳送接收器

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