操作在 4-Gbps 晶片內傳輸電路

4-Gbps On-chip Interconnect Circuit in TSMC 0.18 μm Technology

周宗毅(Tsung-Yi Chou)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.03152

摘要

本論文以一個新的傳輸線架構-挖槽的半同軸線為基礎，並且利用所提出的周邊電路，解決晶片中廣域連結的傳輸問題。此系統使用台灣積體電路公司 0.18 微米製程，經由量測結果證實，可在1.8V峰值到峰值時達到每秒傳輸 4 兆位元以上的資料。此利用傳輸線為基礎的系統，其傳輸速度也比傳統使用中繼器來的快速。

關鍵字

積體電路內部連結 ； 傳輸線 ； 單晶積體電路 ； 晶片內部連結 ； 廣域連結

並列摘要

This work is based on a novel structure of transmission line — slotted semi-coaxial line and adopts the proposed peripheral circuits to solve the problem of global interconnect. This work adopted TSMC 0.18μm technology and it is proved by the measurement results that the proposed structure can transmit up to 4 Gbps data at 1.8V peak-to-peak. The system which adopted the proposed transmission line is also faster than the conventional RC repeater.

並列關鍵字

Integrated circuit interconnections ； transmission line ； monolithic integrated circuits ； on-chip interconnect ； global interconnect

參考文獻

[1] International Technology Roadmap for Semiconductors, http://www.itrs.net 2003.

[2] J. A. Davis, V. K. De and J. D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part I: Derivation and Validation,” IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 580-589, March 1998.

[3] J. A. Davis, V. K. De and J. D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation,” IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 590-597, March 1998.

[6] E. Kyriaskis-Bitzaros and N. Haralabidis, “Realistic End-to-End Simulation of the Optoelectronic Links and Comparison With the Electrical Interconnections for System-On-Chip Applications,” Journal of Lightwave Technology, vol. 19, no. 10, pp. 1532-1541, Oct. 2001.

[7] Ron Ho, Kenneth W. Mai and Mark A. Horowitz, “Efficient On-Chip Global Interconnects,” Symp. VLSI Circuits Dig Tech. Papers, pp. 271-274, June 2003.