連續漸近式類比數位轉換器架構改良之低壓降線性穩壓器

系統晶片會隨著製程、供應電壓定與溫度偏異而產生飄移，電路上會產生非理想的偏異，會造成系統上的不穩定，進而造成晶片的不正常工作，更嚴重而導致晶片的損壞，如何設計出一不隨製程、電壓變異且低功率消耗的穩壓器便是研究中一個重要的議題，在電路設計上使用數位電路才取代誤差放大器，因此，此論文目標為改良之前學長所設計出一個使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器。低壓降線性穩壓器有幾項主要考量的特性參數: (1) 輸出電壓差(△V)與靜態電流(Quiescent Current, Iq) (2) 線性調節率(Line Regulation, LNR) (3)負載調節率(Load Regulation, LDR)；這些參數都與負載電流、精準度、穩壓時間有著密不可分的關係。整體電路可分為三大部分，第一部分為利用8位元連續漸近式類比數位轉換器架構，第二部分為製程變異，而第三部分為智控機制。低壓降線性穩壓器電路的設計，產生一電壓正負誤差10%的電壓與一最低與最高的可承受電流，而這兩電壓與電流經由功率電晶體後，最後輸出還能穩定在固定的電壓，利用連續漸近式類比數位轉換器的訊號來控制功率電晶體以達到穩定的輸出電壓，並且降低在穩態中，所消耗的靜態電流。首先利用製程變異偵測在哪個製成，第二利用比較器來比較輸入電壓與偵測負載來判斷所要增加的電壓給予回授電壓。最後第三點，在設計連續漸近式類比數位轉換器架構和比較器部分，盡量降低DC電流消耗以節省整體的電流消耗。

關鍵字

低壓降線性穩壓器；連續漸近式類比數位轉換器； LDO ； SAR

並列摘要

SoC circuits may produce non-ideal effects due to variations of process, supply voltage, and temperature, which cause the chip not to work or lead to damage the chip in serious. Besides, how to design a low power consumption of the circuit is an important issue. In this thesis, we will design a low dropout (LDO) regulator circuit that uses a successive approximation analog to digital converter to replace the error amplifier. There are several key considerations for low dropout linear regulator characteristic parameters, such as: output voltage difference (ΔV), quiescent current (Iq), linear regulation rate (LNR), and load regulation rate (LDR). These parameters have close relationship with the load current, precision, and settling time of the LDO. The proposed LDO circuit consists of three parts: an 8-bit successive approximation analog-to-digital converter (ADC), a process variation adjuster, and a scanner to scan Vin and the output resistance. The proposed LDO uses the signal from the SAR ADC to control the power transistor to adapt the output voltage and can reduce the quiescent current in the steady state. During the operation, firstly it adjusts the process variation. Secondly, it compares the input voltage and the resistance to control the feedback additive voltage value to the feedback voltage to turn on or turn off the power transistors. Finally, the designed comparators may reduce the DC current.

並列關鍵字

LDO ； SAR ； ADC

參考文獻

[1] Yat-Hei Lam and Wing-Hung Ki. "A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response." 2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers. IEEE, 2008.

[2] Shi, Chunlei, et al. "A highly integrated power management IC for advanced mobile applications." IEEE Journal of Solid-State Circuits 42.8 (2007): 1723-1731.

[4] Chen, C., J. H. Wu, and Z. X. Wang. "150 mA LDO with self-adjusting frequency compensation scheme." Electronics letters 47.13 (2011): 767-768.

[5] Guo, Jianping, and Ka Nang Leung. "A 6-W chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology." IEEE Journal of Solid-State Circuits 45.9 (2010): 1896-1905.

[6] Heng, Socheat, and Cong-Kha Pham. "Improvement of LDO's PSRR deteriorated by reducing power consumption: implementation and experimental results." 2009 IEEE International Conference on IC Design and Technology. IEEE, 2009.

國際替代計量

連續漸近式類比數位轉換器架構改良之低壓降線性穩壓器

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