應用於無線通信系統之連續時間三角積分調變器

Continuous-Time Delta-Sigma Modulator for Wireless Communication Application

陳柏升(Po-Sheng Chen)

指導教授 ： 江正雄

淡江大學/工學院/電機工程學系碩士班/碩士(2010年)

https://doi.org/10.6846/TKU.2010.01280

摘要

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關鍵字

連續時間數位類比轉換器 ； 三角積分調變器

並列摘要

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並列關鍵字

Continuous-Time ADC ； Delta-Sigma Modulator

參考文獻

[1] E. Prefasi, L. Hernandez, S. Paton, A. Wiesbauer, R. Gaggl, E. Pun, “A 0.1mm2, Wide Bandwidth Continuous-Time ΣΔ ADC based on a Time Encoding Quantizer in 0.13μm CMOS,” IEEE J. Solid-State Circuit, vol.44, pp. 2745–2754, Oct. 2009.

[2] M.H. Perrott, M. Park, “A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13μm CMOS” IEEE J. Solid-State Circuit, vol.44, pp. 3344-3358, Dec. 2009.

[3] K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho, A. Matsuzawa, “A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator,” IEEE J. Solid-State Circuit, vol.45, pp. 697–706, 2010.

[4] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2641–2649, Dec. 2006.

[5] B. J. Lucien, R. Robert, and W. Gunnar, “A cascaded continuous-time ΔΣ modulator with 67-dB dynamic range in 10-MHz bandwidth,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2152–2160, Dec. 2004.