兩位元TANOS快取記憶體之低頻雜訊分析

採用薄膜電晶體製程之快取記憶體近幾年被廣泛應用在各種可攜式電子產品中。因其具有低成本、高儲存密度及低功耗等特性，故可應用於系統整合型面板與3D堆疊結構上。本論文採用之結構為兩位元存取之TANOS-TFT記憶體。其結構展現了相當優異的NVM與高儲存密度特性，但長通道的多晶矽TANOS NVM在2位元的寫入/抹除操作(通道熱電子注入與帶對帶穿隧引發熱電洞注入)下，並無法實現2位元的操作需求，故在長通道結構須改採用modulated Fowler–Nordheim (MFN) 寫入/抹除機制來實現2位元的操作。因此本論文主要在探討具雙閘極奈米線結構元件，在MFN與FN寫入抹除操作前、後之低頻雜訊特性與變化。實驗中探討在不同的寫入/抹除操作電壓下的低頻雜訊變化並藉由粹取及探討晶粒邊界陷阱密度(Grain Boundary Trap density, QT)來輔助分析。藉由本論文之研究，能夠了解2位元MFN與FN寫入/抹除機制對於雙閘極TANOS NVM低頻雜訊之影響，使TANOS 記憶體元件之設計提供有利之依據，進而達到優化及降低低頻雜訊的影響，達成實現系統面板之願景。

關鍵字

低頻雜訊；奈米線；氮化鉭-氧化鋁-氮化矽-氧化矽-多晶矽；非揮發性記憶體；兩位元

並列摘要

In recent years, Poly-Si flash memory is extensively utilized in various portable electronic products. Poly-Si flash memory can be applied to system-on-panel (SOP) and 3D circuit applications because of its characteristics of low cost and low power consumption. In this thesis, the NVM utilizes a two-bit TaN-SiO2-Si3N4-SiO2-Si (TANOS)-type thin-film transistor (TFT), which has shown NVM characteristics and ultrahigh storage density. In poly-Si TANOS flash memory devices with a long channel, 2-bit operation is difficult to achieved by channel hot electron injection (CHEI) programing and band-to-band tunneling-induced hot-hole injection (BTBT-HHI) erasing owing to the grain boundaries. Accordingly, modulated Fowler-Nordheim (MFN) tunneling, which requires no charge acceleration, was performed in poly-Si TANOS flash memory for spatial programming and erasing. In this thesis, we would like to study the LFN in dual-gate (DG) TANOS with multiple nanowire (multi-NW) channel structure under modulate Fowler–Nordheim tunneling program/erase (P/E) operation. In addition, grain boundary trap density (QT) were examined to assist in the analysis of LFN for poly-Si TANOS NVM. In conclusion, through this thesis, we would like to provide DG TANOS-TFT design with strong reference to optimize memory by reducing the impact of LFN, and thus achieve the idealization of SOP.

並列關鍵字

LFN ； nanowire ； TANOS ； poly-Si TFT ； Flash memory ； Two-bit

參考文獻

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國際替代計量

兩位元TANOS快取記憶體之低頻雜訊分析

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