本論文第一部分提出最高轉換效率91.5%的直流-直流降壓轉換器,其使用三角積分調變器當作控制迴路。由於三角積分調變器的雜訊移頻與輸出頻率並非固定,因此能有效降低整體雜訊輸出準位。晶片使用台積電0.35-μm互補式金氧半製程來實現。此設計之取樣頻率為5.12 MHz,電感使用4.7 μH而電容為4.7 μF。量測結果顯示此轉換器的負載電流變化為450 mA時,其穩定時間約為60 μs;雜訊準位低於-70 dBm;晶片面積為1.45 x 1.22 mm2。 為了進一步改善控制迴路的低頻雜訊與加快暫態響應速度,本論文第二部分提出具截波三角積分調變技術之低雜訊降壓轉換器。在三角積分調變器內加入截波開關以降低低頻雜訊,並於電路輸出端加入快速迴路到三角積分調變器電路內增快暫態響應速度。晶片使用台積電0.35-μm互補式金氧半製程來實現。此設計之取樣頻率為5.12 MHz,電感使用2.2 μH而電容為4.7 μF。量測結果顯示此轉換器的負載電流變化為450 mA時,其穩定時間約為20 μs;在輸入電壓為3.6 V、輸出電壓為3 V時,全負載效率皆高於85%;負載電流150mA,最高效率為90%;雜訊準位低於-76 dBm;晶片面積1.49 x 1.46 mm2。
In first part, we proposed a delta-sigma based DC-DC buck converter with peak efficiency of 91.5%. We can effectively lower the harmonic tones of converter’s output owing to the noise-shaping and unfixed switching frequency of delta-sigma. The proposed buck converter has been fabricated with a TSMC 0.35 μm CMOS 2P4M process. We design the sampling frequency with 5.12 MHz, the inductor of 4.7 μH and the capacitor of 4.7 μF. Measured results show that the recovery time is about 60 μs for a load step of 450 mA. The noise level is lower than -70 dBm. The chip area is 1.45 x 1.22 mm2。 In order to improve the controller’s low frequency noise and achieve faster transient response, we proposed a low noise buck converter with chopper-stabilization delta-sigma modulator in second part. By adding chopper switches and fast path which is from circuit’s output to feed to delta-sigma modulator in order to lower low frequency’s noise and accelerate the transient response, respectively. The proposed buck converter has been fabricated with a TSMC 0.35 μm CMOS 2P4M process. We design the sampling frequency with 5.12 MHz, the inductor of 2.2 μH and the capacitor of 4.7 μF. Measured results show that the recovery time is about 20 μs for a load step of 450 mA. Average efficiency is above 85% over its full loading range when input/ output voltage equals to 3.6 V/3 V. The peak efficiency is 90% at load current of 150 mA. The noise level is lower than -76 dBm. The chip area is 1.49 x 1.46 mm2。