使用三角積分調變器之降壓型轉換器研製

Study and Implementation of Buck Converter with Delta-Sigma Modulator

趙大瑋(Ta-Wei Chao)

指導教授 ： 陳建中 ； 黃育賢

國立臺北科技大學/電資學院/電資碩士班/碩士(2012年)

https://doi.org/10.6841/NTUT.2012.00606

摘要

本篇論文主要研製了一個降壓型轉換器，其控制電路的架構採用離散時間二階一位元的三角積分調變器，並利用同步整流的方式，減少功率損耗，增加整體效率。三角積分調變器所提供的超取樣與雜訊移頻機制，可有效降低轉換器輸出的雜訊準位，對於後端是射頻、通訊或音頻之應用較有利；使用簡化後的開關電容架構，來使晶片面積下降並使效率提升。轉換器以TSMC 0.35μm DPQM CMOS製程實現，本論文所研製之轉換器具有好的雜訊抑制能力及高轉換效率。實測結果顯示，雜訊準位低於-56dBm；在1.8V~2.5V的輸出，負載電流從50mA到200mA時，效率可達到85%~93.5%。

關鍵字

三角積分調變器 ； 降壓型轉換器

並列摘要

This thesis presents the study and implementation of buck converter whose control circuit architecture uses discrete-time second-order one-bit delta sigma modulator and using synchronous rectification to reduce the power loss increases total efficiency. With oversampling and noise shaping mechanism, delta sigma modulator which can effectively reduce the noise level of the converter output is suitable for RF, audio or communication applications. By using simplified switched-capacitor integrator architecture, the proposed circuit achieves small chip area and high efficiency. The proposed converter which has good noise rejection and high conversion efficiency is fabricated with TSMC 0.35um CMOS DPQM process. Moreover, the measured results show the noise level less than -56dBm and efficiency which output voltage is 1.8~2.5V achieves 85% to 93.5% with a load current range from 50mA to 200mA.

並列關鍵字

Buck converter ； Delta-sigma modulator

參考文獻

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