應用電源層切割、電壓調節模組及去耦合電容抑制Delta-I雜訊分析

Applications of moats, voltage regulator modules and decoupling capacitors on suppressing delta-I noise

洪國強(Guo-Chiang Hung)

指導教授 ： 林丁丙 ； 吳俊德

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2005年)

摘要

本論文主要目標在降低因元件狀態切換時所產生的突波電流雜訊，防止雜訊干擾到其他元件的驅動情形，以及避免直流雜訊對於其他元件的影響。以往的論文有提出許多改善突波電流雜訊的方式，例如利用蝕刻槽線及磁珠元件隔離元件與元件之間突波電流雜訊的干擾等，但如此不僅容易導致電路成本的增加，並且由於磁珠為低通的元件，反而會造成低頻的功率完整性問題。為了改善以上的缺點，本論文提出新的改善方法，主要利用蝕刻槽線將電源層蝕刻成兩個相連的區域，配合去耦合電容以隔離突波電流雜訊的干擾，同時結合了電壓調節模組以抑制直流雜訊的影響，並由模擬及量測結果的一致性中，驗證了此方式的可行性。
本論文之改善結果，可用來說明少量的去耦合電容、蝕刻槽線以及電壓調節模組應用於隔離突波電流雜訊的干擾，具有其潛在的實用價值。

關鍵字

功率完整性 ； 去耦合電容 ； 電壓調節模組

並列摘要

The main purpose of this thesis is to reduce the delta-I noise when the drivers switch from one state to another and prevent noise to interference the state of another component. The DC noise will be improved in this thesis. A large number of structures will be discusses to improve the delta-I noise, i.e. etch slot and put ferrite bead between the component and another component to isolated delta-I noise. This method not only increases the cost of product and the ferrite bead is low pass circuit that will make signal integrity problem. In order to improve the shortcomings mentioned above, this thesis proposes a new improvement method, which will have the metal between two districts on the power plane and around the component by slot. That will put de-capacitors at metal to isolated delta-I noise and use voltage regulator module to improve DC noise. Finally, through the consistency of simulation and measurement the proposed method is available.
The results presented in the thesis show use few de-capacitors、etch slot and put voltage regulator module have a potential value on practical application to improve the effect of delta-I noise.

並列關鍵字

power integrity ； decoupling capacity ； voltage regulator module

參考文獻

[1] Yuzhe Chen, Zhonghua Wu, A. Agrawal, Yaowu Liu, Jiayuan Fang, “Modeling of Delta-I noise in digital electronics packaging,” IEEE Multi-Chip Module Conference, pp. 126 – 131, Mar. 1994.

[2] G. Katopis, B. Singh, W. Becker, H. Smith, “Delta-I modeling approximation for single chip modules,” IEEE Electrical Performance of Electronic Packaging, pp. 111 – 113, Oct. 1996.

[3] L.D. Smith, R.E. Anderson, D.W. Forehand, T.J. Pelc, T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, pp. 284 – 291, Aug. 1999.

[4] Hsiao-Ping Tsai, “Impact of high impedance mid-frequency noise on power delivery,” Electrical Performance of Electronic Packaging, pp. 125 – 128, Oct. 2003.

[5] Hao Shi; Jun Fan; J.L. Drewniak, T.H. Hubing, T.P. Van Doren, “Modeling multilayered PCB power-bus designs using an MPIE based circuit extraction technique,” IEEE International Symposium on Electromagnetic Compatibility, vol. 2, pp. 647 – 651, Aug. 1998.