透過您的圖書館登入
IP:216.73.216.144
  • 學位論文

適用於十億位元乙太網路系統之 10位元125MHz數位發射器

10-bit 125MHz Digital Transmitter for Gigabit Ethernet

指導教授 : 宋國明
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


本論文旨在製作一適用於十億元乙太網路系統(Gigabit Ethernet),且操作頻率為125 MHz之CMOS數位發射機,主要包含有10位元125 MHz之數位類比轉換器及電流模式全差動線驅動器兩個部份,並採用TSMC 0.18 μm 1P6M CMOS製程技術來實現。 為了達到高速操作頻率的需求,故採用電流切換式之數位類比轉換器架構。本論文參考一個電流源偏壓技巧於電流源的實現,藉以改善臨界電壓漂移與電源導線壓降所造成的電流誤差。再利用緩衝器的概念,於電流源的輸出端加上一緩衝器以降低突波現象。此外,為了將數位電路之佈局面積與複雜度、操作速度及差動非線性誤差(Differential Nonlinearity Error)做最佳化之設計考量,本論文另採用一個等效於八位元之溫度計碼(Thermometer Code)解碼架構,在佈局方面,為了消除線性和拋物線梯度誤差,因此採用四象限對稱的電流源佈置。 就線驅動器而言,為了得到較高的功率效益(Power Efficiency),分別利用兩條不同的電壓源路徑,以避免電壓源路徑疊加,藉以實現低電壓的電路設計,以及採用合成(Synthesis)的方式,此合成電路能產生輸出阻抗匹配電阻,藉以降低電路的功率消耗、提升功率效益。此外,本論文進而利用濾波電容及對大寄生電容端點提供前饋的充放電路徑以及線驅動器後級加上電流回授補償電路,以抑制諧波失真問題,並提高線性度。本線驅動器在1.8 V的供應電壓下,能驅動100 Ω輸出端負載,產生125 MHz與2 VPP的電壓訊號振幅。

並列摘要


This thesis describes the implementation of a 125 MHz CMOS digital transmitter, which is composed of a 10-bit, 125 MHz digital to analog converter, and a fully differential current-mode line dirver, which is based on Gigabit Ethernet system specification. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. For high-speed application, the digital to analog converter adopts the current switch mode architecture. In order to reduce the current error and threshold-voltage variation, we use a current-source biasing technique. Buffers are used to isolate the output of digital circuit and glitch on current source could be reduced. Furthermore, in the cause of achieve smaller layout area, reduce the complexity of digital circuit and decrease the differential nonlinearity error (DNL). The digital-to-analog converter consists of 8-bit thermometer-encoding architecture. For the line driver achieve, in order to got high power efficiency, the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is used to reduce the crossover distortion and the current-feedback circuit is added to line driver to increase linearity. The line driver over a 100 Ω differential load at 1.8V power supply and in 125 MHz operating frequency, the output voltage swing of the line driver is 2 VPP.

參考文獻


[31] 姚學儒,切換電容式三角積分調變器設計與實作,碩士論文,國立台北科技大學電機工程系研究所,台北,2007。
[1] D. A. Johns and D. Essig, “Integrated Circuits for Data Transmission Over Twisted- Pair Channels,” IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 398–406, March 1997.
[2] M. Pelgrom, “A 50 mhz 10-bit CMOS Digital-to-Analog Converter with 75 ohm Buffer,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1990, pp. 200–201.
[3] D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997.
[4] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948–1958, December 1998.

被引用紀錄


周文敦(2013)。適用於VDSL之12位元200MHz倍取樣率數位發射器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2013.00481
卓儒宏(2011)。適用於VDSL之12位元數位發射器〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-0908201116400600

延伸閱讀