65 nm節點PMOSFETs之熱載子及負偏壓溫度不穩定性效應

Hot-Carrier and Negative Bias Temperature Instability Effects on 65 nm Node

吳柏毅(Po-Yi Wu)

指導教授 ： 黃恆盛 ； 陳雙源

國立臺北科技大學/機電學院/機電整合研究所/碩士(2009年)

https://doi.org/10.6841/NTUT.2009.00508

摘要

熱載子(hot-carrier, HC)效應一直是主要的可靠度研究課題。在早期的研究中，HC的最劣化情形是在室溫時之汲極雪崩熱載子(DAHC)模式，然而在近幾年的研究指出最劣化情形改變為通道熱載子(CHC)模式，並在溫度方面也由低溫變成高溫。另外，在0.13微米製程之後，為了減少漏電流，並且抑制硼滲透，使用氮矽氧化物(SiON)作為閘極介電層。然而使用氮矽氧化物的pMOSFET，其負偏壓溫度不穩定性(negative bias temperature instability, NBTI)已成為另一項嚴重的可靠度問題。了解HC和NBTI效應造成現今元件劣化的程度是一項重要的課題。而在之前實驗室的成果中，以經確認NBTI和元件的閘極氧化層厚度有關。在本實驗中想去了解不同臨界電壓的元件(尺寸相同)是否和元件劣化有關。
實驗使用聯華電子公司(UMC)所提供的測試晶片。而研究主要分為以下幾個部份，第一部份，探討65奈米製程元件，不同臨界電壓掺雜濃度下，在pMOSFET的NBTI和CHC效應；第二部份，利用模型預估元件的壽命；最後，觀察並比較65奈米製程pMOSFET可靠度測試的劣化程度。
在實驗中，可觀察到臨界電壓掺雜濃度對CHC所造成的劣化有輕微的相關性，在較高的臨界電壓掺雜濃度下，有較低的CHC劣化。但是在NBTI中，並沒有完全依照這樣的趨勢。最後，在比較pMOSFET的CHC和NBTI的劣化程度，發現NBTI的劣化程度和CHC相比，在高溫下已有越來越嚴重的趨勢。

關鍵字

熱載子 ； 負偏壓溫度不穩定性 ； 65奈米

並列摘要

Hot carrier (HC) effect has been the major reliability issue to study. In early researches, HC showed the worst degradation at DAHC mode low temperature. However, a recent study reported that the worst case has switched from DAHC to CHC mode and from low to high temperature. Furthermore, after the introduction of 0.13-μm technology node, oxynitride (SiON) dielectric became the proposed dielectric material to reduce the leakage current and suppress the boron penetration. At the same time, negative bias temperature instability (NBTI) in pMOSFET device is now widely recognized as one of the most critical reliability concerns and is enhanced by inclusion of nitrogen in gate dielectrics. Therefore, understanding the degree of degradation which is influenced by CHC and NBTI would become an important issue. In the previous laboratory results, it has recognized that NBTI induced degradation is related to the oxide thickness. In this test, we wanted to know that the different Vt implant effect the degradation of device which is under NBTI and CHC stress.
In this research, the wafer which is from United Micro-electronics Corporation (UMC) would be used to explore the reliability issues. The study would be divided into the following parts. The first one is to investigate the NBTI and CHC effect on 65 nm node pMOSFETs which have different Vt implant. Then, we used the lifetime model to predict the device lifetime. Finally, pMOSFET would be observed and compared to detect the worst reliability case.
In this study, the CHC stress induced degradation was slightly related to Vt implant. The CHC induced degradation was decreased as the Vt implant increased. However, under NBTI stress, the degradation would be not completely related to Vt implant. Finally, compared with the CHC induced degradation, NBTI induced degradation would be more and more serious at high temperature.

並列關鍵字

Hot-carrier ； NBTI ； 65 nm

參考文獻

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