以反向器為基礎之類比式LDPC解碼器晶片設計

Chip Design of an Inverter-based Analog LDPC Decoder

邱凱增(Kai-Tzeng Chiou)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2013年)

https://doi.org/10.6841/NTUT.2013.00681

摘要

典型的類比式LDPC解碼器內部使用到疊接電流鏡(Cascade Current Mirror)，但隨者製程的進步，標準操作電壓卻沒有隨者降低。因此許多疊接電路並不適合使用在深次微米的製程，本論文提出一個以反向器為基礎之類比式LDPC解碼器，基本上我們將類比用的位元節點與檢查節點均以反向器作為基本元件，所做出來的電路，可以進行數位合成、可以壓抑隨機不匹配的情況、可以應用於低操作壓電路等優點。
最後在驗證上，本論文實際使用TSMC 0.18-μm 1P6M CMOS製程技術，完成一顆(8,4)類比式LDPC解碼晶片製作，晶片的標準操作電源電壓為 1 V，總共有1,452顆電晶體，整個晶片面積為0.696 × 0.696 mm2，其吞吐量為26.67 Mbps，功率消耗為0.5 mW。實驗結果顯示該一解碼晶片，具有低功率消耗、低操作電壓的優點，並可供System on Chip (SoC) 之相關運用。

關鍵字

類比式解碼器 ； 反向器 ； 最小和演算法 ； 低密度奇偶檢查碼

並列摘要

The traditional analog LDPC decoder is composed of cascade current mirrors. However, processes are advancing, but the standard power supply is not decreased. Hence, many cascade circuits are not suitable for sub-micro processes. In this thesis, an inverter-based analog LDPC decoder is presented. Basically, the inverters are the basic components of bit nodes and check nodes. The inverter-based architecture has many advantages which include suppressed random mismatch, digital synthesis, and low-power supply.
Finally, the analog (8,4) LDPC decoder is designed and examined by TSMC 0.18-μm 1P6M CMOS technology in this thesis. The standard power supply is 1 V. The proposed decoder includes 1,452 MOSFETs. The chip area is 0.696 × 0.696 mm2, and data throughput is 26.67 Mbps. The power dissipation is 0.5 mW in the measured result. Finally, the measurement results show that the proposed decoder has the advantage of the low power dissipation and the low supply voltage. It is suitable for related SoC application.

並列關鍵字

Analog Decoder ； Inverter ； Min-Sum Algorithm ； LDPC

參考文獻

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