具提早終止疊代之新型類比式低功率LDPC和積解碼器晶片設計

Chip Design of an Analog Low Power Sum-Product LDPC Decoder using Early Termination

柯玉璽(Yu-Shi Ke)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2013年)

https://doi.org/10.6841/NTUT.2013.00370

摘要

本論文提出一新型低功率且具有提早終止疊代的類比LDPC 解碼器製作，在作法上，我們以和積演算法為基礎並且透過H 校驗矩陣(H-matrix)的判別來實現類比式停止疊代方法。我們提出的解碼器只要1.2V 的供應電壓，可大幅降低解碼器76%的功率消耗。且因加入提早終止疊代的功能更使得資料吞吐量有效的提升。當平均資料吞吐量是31.72Mbps 時，其能源效率值為7.57J/b. 最後我們採用TSMC 0.18μm 1P6M CMOS 製程實現該一新型解碼器。該晶片電晶體數目為2490顆，面積不包含I/O Pad 為0.08mm2。實驗結果顯示該一新型類比解碼器擁有極低的能源效率值和極低的晶片面積，可供運用於新型行動裝置及未來SoC 系統上。

關鍵字

類比解碼器 ； LDPC ； 低功率 ； 停止疊代

並列摘要

This thesis proposes an analog low power LDPC decoder employing new stopping iteration method. It is based on the sum-product algorithm and by checking parity H-matrix to decide iteration termination. The supply voltage of the proposed decoder only uses 1.2V not 1.8V, so the power consumption can be reduced significantly, and then 76% power consumption is saved. Moreover, the early termination method is used. It not only can increase the decoding throughput but also save the power consumption. With these improvements, a very low energy efficiency 7.57pJ/b is obtained when throughput is 31.72Mbps. Finally, an analog low power sum-product LDPC decoder using early termination is implemented by TSMC 0.18μm 1P6M CMOS technology. The chip size is only 0.08mm2 without I/O pad and gate count is 2490. The proposed decoder has very low energy efficiency and low chip area characteristics. So it can be applied to the mobile devices and SoC system.

並列關鍵字

Analog Decoder ； LDPC ； Low Power ； Early Termination

參考文獻

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