停止疊代機制常見於數位式解碼器中,在類比式解碼器中較無學者研究,因此本論文提出一個類比式停止疊代最小和解碼器晶片,此解碼器的電路是以低密度同位元校驗碼為基本架構,並以電流模式電路來完成,為減少硬體複雜度,演算法使用最小和演算法。由於低密度同位元校驗碼解碼器演算法為疊代運算,因此疊代的次數將對整體解碼器影響非常大。所以我們也提出一個具有停止疊代功能的類比解碼器,除了可在吞吐量及解碼效能有效提升外,同時也降低了整體的功率消耗,與典型的解碼器在功率速度比下,可有效地減少90%的消耗。 最後,我們將所提出的類比式停止疊代(32,8)最小和解碼器,以TSMC 0.18μm 1P6M CMOS 製程技術設計實體驗證,此晶片包含20125顆電晶體,其工作電壓為1.8V,平均解碼吞吐量為216-Mb/s,平均功率消耗為4.98mW,功率速度比為0.02nJ/b,整個晶片面積為1.213 × 1.213 mm2,不含I/O PAD面積為0.64 mm2。
The stopping iteration method is wildly used in digital decoder design; however, there are few analog decoders employ this method. Hence, we propose an analog min-sum decoder with stopping iteration method that has advantages on throughput, decoding performance, and power consumption speed ratio. Our decoder is based on LDPC codes and the min-sum algorithm, and we use the current mode circuit to implement design. Experimental results show that our decoder can save 90% power consumption speed ratio compared with traditional decoder. The proposed analog min-sum (32,8) decoder with stopping iteration method is implemented by using TSMC 0.18μm 1P6M CMOS technology. The core size is 0.64 mm2 with 20125 transistors. The operation voltage of our decoder is 1.8V and can achieve 216Mb/s throughput while power consuming 4.98 mW.