- 學位論文
類比改良補償式最小和低密度同位元校驗碼解碼器晶片設計
Analog IC Design of Modified Offset Min-Sum LDPC Decoder
摘要
補償修正法常應用於許多數位解碼器中以提升解碼效能，而在類比解碼器中較為少見，因此本論文將以低密度同位元校驗碼為基本架構，採電流模式電路來實現，為減少硬體複雜度，演算法使用最小和演算法，並且運用改良型補償參數β技術，以改善最小和演算法在簡化過程中所造成的效能損失，進而驗證補償修正法可以應用在類比最小和解碼器晶片之可行性。 最後，我們將所提出的類比改良補償式最小和低密度同位元校驗碼解碼器，以TSMC 0.18μm 1P6M CMOS 製程技術設計實體驗證，此晶片包含2562顆電晶體，其工作電壓為1.8V，平均解碼吞吐量為52.8Mb/s，功率消耗為1.26mW，功率速度比為0.024nJ/b，不含I/O PAD面積為0.07 mm2。結果顯示該一解碼晶片具有低功耗以及面積小的特性，有利於日後整合於小型的手持產品中。
並列摘要
Offset correction methods are often applied to digital decoders for increasing performance, but rare in analog decoders. Thus, based on low-density parity check code, an analog LDPC decoder with current mode is designed in this thesis. Moreover, in order to reduce hardware complexity, an modified offset parameter β is proposed to improve the decoding performance loss caused by simplified Min-Sum algorithm and thus it shows that the offset correction method can be applied to the Min-Sum algorithms and analog decoder chips. Finally, the modified offset min-sum LDPC decoder is implemented using TSMC 0.18μm 1P6M CMOS technology. This chip includes 2562 transistors, supply voltage 1.8V, average decoding throughput 52.8 Mb/s, power consumption 1.26mW. Its’ power speed ratio is 0.024nJ/b and chip area is 0.07mm2 without I/O PAD. Experimental results show that the proposed chip has the characteristics of low power consumption and small area characteristics that is applicable to small handheld products.