類比式和積規則型低密度奇偶檢查碼解碼器晶片設計

IC Design of an Analog Sum-Product Decoder for Regular LDPC Codes

車建樑(Jian-Liang Che)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2011年)

https://doi.org/10.6841/NTUT.2011.00322

摘要

早期就有國外學者提出因為操作於機率域的和積演算法解碼器在硬體的實現上會有成本過大的問題，故在實現上較為不易。因此本論文提出以非疊接式吉爾伯特乘法器所建構之類比式和積規則型低密度奇偶檢查碼解碼器之積體電路設計。此類比式解碼器是以低密度奇偶檢查碼作為電路設計基礎，並採用非疊接電流式吉爾伯特乘法器來實現和積演算法，並完成整個類比式和積規則型低密度奇偶檢查碼解碼器，使其在硬體的實現上可以有效的降低成本過高之問題。
　　最後本文共提出了兩種解碼器晶片，皆以TSMC 0.18μm 1P6M CMOS製程加以驗證。第一顆晶片包含了3932顆電晶體，其工作電壓為1.8V，晶片面積不含I/O PAD為0.1mm2，當資料吞吐量(Throughput)為8.48Mbps時，功率為1.105mW。第二顆晶片改為陣列式架構，共包含了2600顆電晶體，其工作電壓為1.8V，晶片面積不含I/O PAD為0.083mm2，當資料吞吐量為16Mbps時，功率為0.939mW。

關鍵字

類比式解碼器 ； 電流式電路 ； 和積演算法 ； 低密度奇偶檢查碼

並列摘要

In this thesis, we propose an analog sum-product decoder based on Low-Density-Parity-Check (LDPC) codes, and use Gilbert multipliers to realize the function of Sum-Product algorithm. Literatures show that the traditional LDPC decoders working at the probability domain have a major demerit on the chip’s area. Therefore, we propose a non-splice Gilbert multiplier that can decrease the chip’s area for analog sum-product LDPC decoders.
We have implemented two (8, 4) LDPC Sum-Product decoders with TSMC 0.18μm 1P6M CMOS technology and operating at VDD = 1.8V. The first decoder core size is 0.1mm2 including 3932 transistor counts, and the throughput is 8.48Mb/s while power consuming 1.105mW. The second decoder modifies the former chip’s circuits so that has a smaller core size and less transistor counts. The core size of second decoder is 0.083mm2 including 2600 transistor counts, and the throughput is 16Mb/s while power consuming 0.939mW.

並列關鍵字

Analog Decoder ； Current Mode Circuit ； Sum-Product Algorithm ； LDPC

參考文獻

[27] 張繼偉，類比式最小和遞迴解碼器晶片設計，碩士論文，國立台北科技大學，電腦與通訊研究所，民國99年。

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