摘要
本論文提出一個以低功率以及低製造成本為訴求的類比式最小和遞迴解碼器之超大型積體電路架構設計。此類比式最小和遞迴解碼器的電路架構是以低密度同位元校驗碼為設計基礎，並採用電流模式電路來實現它。由於電流傳送的精確度對於整體解碼效能影響非常大，所以我們提出一個新型的變數節點架構，能有效的提升電流傳送的精確度，同時也降低了整體的功率損耗，以及晶片面積。另一方面我們也提出一個低功率的最小值贏者通吃電路，與典型的最小值贏者通吃電路相比，約可節省40%的功率損耗。 最後我們將所提出的類比式最小和遞迴解碼器，以TSMC 0.18μm 1P6M CMOS 製程技術設計驗證，此晶片包含12100顆電晶體，其工作電壓為1.8V，在解碼速度為10-Mb/s時功率消耗為4.3mW，整個電路不含I/O PAD的面積為0.46 × 0.41 mm2。我們所設計的晶片有著低功率以及小面積的特性，有利於日後整合於小型的手持式產品中。
並列摘要
In this thesis, a low power and low cost analog min-sum iterative decoder for VLSI architecture design is proposed. The analog min-sum iterative decoder is devised based on LDPC code that can be implemented by current mode circuit. Because the current precision will affect the decoding performance, we proposed a novel architecture of variable node. The proposed architecture of variable node has the high accuracy characteristic, and furthermore it can reduce the power consumption and chip area. In addition, we proposed a low power minimum WTA circuit, compared to traditional minimum WTA circuit, the proposed WTA circuit can save roughly 40% average power consumption. Finally, the proposed analog min-sum iterative decoder is designed by using TSMC 0.18μm 1P6M CMOS technology. 12100 transistors are used in this chip. When the data throughput and supply voltage is 10 Mb/s and 1.8V respectively, the power consumption is only 4.3 mW. The core size is 0.189 mm2. This analog decoder has low power and small area characteristics that is applicable to portable devices.