- 學位論文
類比式停止疊代正規化對數和積低密度同位元檢查碼解碼器晶片設計
Analog IC Design of Normalized Log Sum-Product LDPC Decoder with the Stopping Iteration Method
摘要
本論文提出一新型類比式停止疊代正規化對數和積LDPC解碼晶片設計。在低密度同位元校驗碼中以和積演算法、對數和積演算法及最小和演算法最為常見，在考量解碼效能及硬體複雜度後，本論文採用對數和積演算法來設計電路並以電流模式來實現，同時提出了一新型正規化類比解碼器，藉由正規化的調整能有效提高對數和積演算法解碼效能；在解碼速度上，亦增加了停止疊代判斷機制來提高其吞吐量。 最後本論文所提之新型類比式正規化對數和積解碼晶片，以TSMC 0.18μm 1P6M CMOS製程加以驗證。第一顆晶片包含了2436顆電晶體，晶片面積不含I/O PAD為0.055mm2，當資料吞吐量為11.85Mbps時，消耗功率為0.78mW。第二顆晶片新增停止疊代架構，共包含了2694顆電晶體，晶片面積不含I/O PAD為0.078mm2，當資料吞吐量為62Mbps時，消耗功率為0.85mW。實驗結果顯示，本論文所設計之解碼架構，不僅具有低複雜度，更有助於提升電路解碼速度，同時也提高了其解碼效能，可供未來通訊系統及SoC之運用。
並列摘要
In this thesis, we propose a new analog normalized log sum-product LDPC decoder with the stopping iteration method. The common LDPC decoding algorithms are the sum-product, log sum-product algorithm and the min-sum algorithm. For decoding performance and circuit complexity consideration, the log sum-product algorithm with current-mode is used in our design. Moreover, a new normalization method is proposed to improve log sum-product algorithm error-correcting performance, and a stopping iteration circuit to increase the throughput. Finally, the proposed LDPC Log Sum-Product decoders are implemented with TSMC 0.18μm 1P6M CMOS technology. The first decoder core size is 0.055mm2 including 2436 transistor counts, and the throughput is 11.85Mb/s while power consuming 0.78mW. The core size of second decoder with stopping iteration is 0.078mm2 including 2694 transistor counts, and the throughput is 62Mb/s while power consuming 0.85mW. Experimental results show that the analog decoders have smaller area and higher throughput, which can be applied to future communication systems and SoC applications.