免額外逆向遞迴運算延遲渦輪解碼器設計

Dummy-Beta-Latency-Free Turbo Decoder Design

葉凌帆(Ling-Fan Yen)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

渦輪碼是一種前向錯誤更正碼，利用大量的運算與多次的疊代來達到接近夏農極限的錯誤更正效能。但傳統渦輪解碼在硬體的實現上需要使用到大量的記憶體，而且解碼輸出延遲時間也比較長。為此本論文藉由分析研究渦輪演算法與滑動視窗演算法，提出一種新型免額外逆向遞迴運算延遲演算法，該一方法可以將解碼延遲由傳統四個L長度縮短成只用一個滑動視窗解碼延遲。在硬體的實現上，此一新架構僅需增加一個額外的記憶體即可省去一個逆向遞迴計算單元和二個內部暫存記憶體。相較於傳統的架構，使用本篇論文所提出的演算法，可在SISO的部份省去27%~45%的記憶體位元數，而在實際記憶體的面積上也可省去65%~68%。為了檢驗此架構的可行性，我們先使用了Xilinx FPGA HW-V4-ML402-USA加以驗證，最後我們也將此一架構以TSMC 0.18 μm 1P6M製程實際完成一顆低延遲渦輪解碼晶片設計，實驗顯示此一解碼器時脈為104.1MHz，整個電路含I/O PAD的面積是1.9 mm 1.9 mm，可供未來無線通訊IP之應用。

關鍵字

渦輪碼 ； 低延遲 ； SISO設計

並列摘要

Turbo code is a forward error correct code which has good error correction capability and near Shannon limiting performance. Traditional turbo decoder needs large memory size and has long decoding latency for implementation. This paper presents a dummy-beta-latency-free algorithm which can reduce the decoding latency of sliding window from 4L to 1L. In hardware implementation, we can use a dummy-beta memory unit to replace one backward calculation unit and two SISO sub-memories. Experimental results show that our architecture can save 27%~45% memory bit and 65%~68% memory area. Then, we have verified this algorithm using Xilinx FPGA (HW-V4-ML402-USA) system. Finally, a dummy-beta-latency-free turbo decoder is designed using TSMC 0.18μm 1P6M CMOS technology. The chip occupies 1.9mm 1.9mm and has a clock frequency of 104.1Mbps.

並列關鍵字

turbo code ； low latency ； SISO decoder

參考文獻

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