結合矽鍺通道與矽鍺源/汲極之應變pMOSFETs特性分析與熱載子效應

Characteristics and Hot-Carrier Effect of Strained pMOSFETs with SiGe Channel and SiGe Source/Drain Stressors

紀良儒(Liang-Ru Ji)

指導教授 ： 黃恆盛 ； 陳雙源

國立臺北科技大學/機電學院/機電整合研究所/碩士(2012年)

摘要

嵌入式矽鍺源/汲極(Embedded SiGe S/D)應變技術，是將源汲極的矽蝕刻至一特定深度後，再重填矽鍺原子。它利用矽與鍺原子晶格不匹配，使矽通道產生一個壓縮應力，此壓縮力能使電洞的載子遷移率增加，進而使P型電晶體的性能提升。雖然已有文獻探討嵌入式矽鍺源/汲極對pMOSFETs的影響，但鮮少有文獻探討雙軸應變結合嵌入式矽鍺源/汲極應變技術的電晶體特性。所以本篇論文的重點在研究，雙軸應變結合嵌入式矽鍺源/汲極應變的電晶體，對於不同通道長度的pMOSFETs性能的影響，並且探討短通道中的熱載子效應。
經由本研究發現，當P型電晶體為長通道時，雙軸應變為主要提升載子遷移率的因素，這應是由於雙軸應變在長通道中產生較大的應力，但是當通道長度縮短時，雙軸應變提升載子遷移率的效果也隨著通道長度縮短跟著變小，這現象會降低電晶體性能提升的效果。不過嵌入式矽鍺源/汲極單軸應變，經本研究證實，可以在短通道中產生較大的壓應力，使載子遷移率能在短通道中增加。因此在電晶體尺寸不斷地微縮之下，利用嵌入式矽鍺源/汲極應變技術來提升電晶體性能是個不錯的選擇。
本研究也針對結合雙軸與嵌入式矽鍺源/汲極應變技術的pMOSFETs元件做熱載子可靠度的測試，計算介面狀態(interface state)的變化量。從實驗數據來看，嵌入式矽鍺源/汲極應變技術的pMOSFETs元件，在高溫的熱載子可靠度測試下，飽和電流劣化約5.5%，比傳統元件飽和電流4.8%的劣化更為嚴重，此劣化較嚴重的原因可能是因為重填SiGe時使介面產生大量的缺陷，導致較嚴重的劣化。因此若要使用雙軸與嵌入式矽鍺源/汲極應變技術的pMOSFETs元件需考慮性能較容易劣化的問題。

關鍵字

應變矽 ； 嵌入式矽鍺源/汲極 ； 雙軸應變 ； 熱載子效應

並列摘要

The embedded SiGe S/D stressor involves etching out the source/drain silicon and replacing it with SiGe. It uses the lattice mismatch between silicon and germanium atoms which makes the silicon channel generating compressive strain. The compressive stress enhances hole mobility, and the pMOSFETs performance can be enhanced.
Previous literatures have investigated the effects of pMOSFETs with embedded SiGe S/D stressor, but devices incorporated with biaxial strain and embedded SiGe S/D has not been clearly investigated. In this work, we research the characteristics of devices containing biaxial strain and embedded SiGe S/D stressor with different channel lengths and explores the channel hot carrier (CHC) in short channel pMOSFETs.
The experimental results show that the biaxial strain achieved higher carrier mobility in long channel. It is believed that the biaxial strain induced larger stress. However, the biaxial strain reduces its mobility enhancement effect when the channel length becomes short. In contrast, the experiment also shows that the embedded SiGe S/D stressor can enhance carrier mobility by increasing compressive stress in short channel. Therefore, the embedded SiGe S/D stressor is a good choice for enhancing drain current when the conventional MOSFETs step deeper into the nano-regime.
The reliability of channel hot carrier (CHC) for pMOSFETs with combination of biaxial and embedded SiGe S/D stressors is also investigated. The enhancement of interface states is also calculated. From our high temperature experimental results, saturation current of the embedded SiGe S/D pMOSFETs degraded 5.5%, which is more serious than Si-control devices’ 4.8% degradation. It is presumable that embedded SiGe S/D induces more traps in the interface. Therefore, using the combination of biaxial and embedded SiGe S/D strain devices, performance degradation problem should be considered carefully.

並列關鍵字

Strained-Si ； embedded SiGe Source/Drain ； biaxial strain ； hot-carrier effect

參考文獻

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