以0.18um CMOS積體電路技術研製5.2GHz鏡像抑制混頻器

The Study and Implementation of 5.2GHz Image-Rejection Mixer With 0.18um CMOS IC Technology

何俊慶(Jun Qing He)

指導教授 ： 楊正任 博士

元智大學/工程學院/電機工程學系/碩士(2002年)

摘要

本論文主要是以0.18um CMOS製程，來完成5.2GHz鏡像抑制混器之設計。以往的射頻電路晶片，多是以GaAs及Bipolar製程為主，雖然此兩種製程操作在高頻時，會比CMOS製程具有更好的特性。但是由於基頻電路部分，多是以CMOS來實現。故在系統單晶片整合方面，CMOS較具優勢。也因此，CMOS射頻電路越來越受重視。
論文中的混頻器，乃是針對802.11a規格來做電路設計，以期符合下一代無線區域網路標準。在電路方面，採用Hartley架構來設計鏡像抑制混頻器，並且利用Ansoft Harmonica軟體來模擬電路之各項特性。且透過國家晶片系統設計中心(CIC)的協助，使用台積電0.18um製程來實際製作此晶片。最使用PCB測試電路來實際量測此晶片之真實特性。而在Hartley架構中，RC-CR電路頻寬不足所產生的問題，我們也採用了Polyphase Filter電路來作模擬，以改善其頻寬。此晶片面積大小為0.739mm×0.5928mm。

關鍵字

混頻器 ； 混波器 ； 鏡像抑制

並列摘要

In this thesis we use 0.18um CMOS process to design a 5.2GHz Image-rejection Mixer. In the past, the Radio Frequency circuit chip was always implemented in GaAs or Bipolar processes. Although they have much better quality than CMOS process at high frequency, but the baseband circuits always use CMOS process. In order to integrate the whole receiving circuits into a single chip, the RF CMOS circuits have become more important in wireless products.
The circuit design of mixer is to be aimed at the specification of IEEE 802.11a standard in this twork. We use Hartley architecture to deign an Image-Rejection mixer. We also simulate the characteristic of Hartley Image-Rejection mixer by using the simulation tool “Ansoft Harmonica”. With the help of NSC Chip Implementation Center, we used TSMC 0.18um CMOS process to realize the circuit. Finally, we measured the electric performance of this chip by using PCB testing circuit. Besides, we introduce Polyphase Filter circuit to improve the bandwidth of RC-CR network. The chip size of total circuit is about 0.739mm×0.5928mm.

並列關鍵字

mixer ； image rejection ； hartley ； polyphase ； CMOS ； Gilbert cell

參考文獻

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