運用三角積分調變技術之5.8-GHz小數-N頻率合成器

A 5.8-GHz Delta-Sigma Fractional-N Frequency Synthesizer

陳威良(Wei-Liang Chen)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2003年)

摘要

在本論文中一個運用三角積分調變技術的5.8-GHz小數-N頻率合成器被分析、設計並以台積電0.25um 1P5M CMOS製程實現。考量低成本與低功率損耗的目的，此頻率合成器整合一個低功率高效率壓控振盪器、一個入射鎖定頻率除頻器和一個全數位管線化三階的MASH三角積分調變器。另外，此頻率合成器在使用一個35MHz的參考訊號源下擁有300KHz的迴路頻寬，整體閉迴路相位雜訊可達到約-80dBc/Hz且使用一個2.5V的電源供應整體功率損耗約33mW。因為使用小數-N鎖向迴路的架構，使得此頻率合成器可以提供頻率解析度高於25KHz而其迴路鎖定時間約為13us，適用於IEEE 802.11a 無線區域網路5.8-GHz頻段的應用 ─ 如用於射頻前端電路中的一個本地振盪源。
一個5.8-GHz壓控振盪器測試晶片量測結果也附於本文中，此晶片量測結果顯示此壓控振盪器在相對主頻率1MHz偏移量可達最佳約-110dBc/Hz的相位雜訊表現。

關鍵字

CMOS ； 壓控振盪器 ； 三角積分調變 ； 鎖相迴路 ； 小數-N ； 頻率合成器

並列摘要

In this thesis, a 5.8-GHz delta-sigma fractional-N frequency synthesizer is analyzed, designed and implemented in TSMC 0.25um 1P5M CMOS process. In consideration of low cost and low power, the synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider (ILFD) and a digital pipelined third-order MASH delta-sigma modulator together. It has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about—80dBc/Hz while the total power consumption is 33mW from a single 2.5V supply. With the fractional-N architecture, this synthesizer can provide frequency resolution finer than 25KHz and the locking time is about 13us which is suitable for the IEEE 802.11a WLAN applications such as a local oscillator in RF receiver front-end.
Some measurement results of VCO testing prototype are also presented where the VCO exhibits a phase noise performance of about —110dBc/Hz at 1MHz offset from the center frequency.

並列關鍵字

CMOS ； Voltage-Controlled Oscillator ； Delta-Sigma Modulation ； Phase-locked Loops ； Fractional-N ； Frequency Synthesizer

參考文獻

[1] K. Pahlavan, A. Zahedi and P. Krishnamurthy, “Wideband local access: Wireless LAN and wireless ATM,” IEEE Commun. Mag., pp.34-40, Nov. 1997.

[2] C. Lam and B. Razavi, “A 2.6GHz/5.2GHz frequency synthesizer in 0.4um CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788-794, May 2000.

[3] H. Rategh, H. Samavati, and T. H. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, pp. 780-787, May 2000.

[4] X. Yang, T. Wu, and J. McMacken, “A 5GHz fast-switching frequency synthesizer,” IEEE Radio Frequency Integrated Circuits Symposiums, pp. 479-482, 2002.

[5] S. Ali and F. Jain, “A low jitter 5.3GHz 0.18um CMOS PLL based frequency synthesizer,” IEEE Radio Frequency Integrated Circuits Symposiums, pp. 173-176, 2002.