應用於無線數位通訊次諧波混頻器之設計、製作和測試

Design、Implementation and Testing of Sub-harmonic Mixer for Wireless Digital Communication

戴文彬(Wen-Pin Tai)

指導教授 ： 黃建彰 博士

元智大學/工程學院/通訊工程學系/碩士(2004年)

摘要

無線通訊射頻前端接收架構中，混頻器直接影響整個接收機的動態範圍大小，亦式無線通訊的關鍵性零組件之一。本論文模擬設計頻IEEE 802.11a頻段的次諧波混頻器並以CMOS電路來實現，利於將來作系統整合晶片(SOC)及低成本的考量。
論文第一部分了解混頻器在於接收機中的影響與設計上的重要的參數。第二部分是使用TSMC 0.18um CMOS製程技術及利用Agilent ADS電路模擬軟體，設計雙閘極混頻器、二倍頻及次諧波混頻器。第三部分是加強型分立式高電子遷移率電晶體(E-pHEMT)做為主動元件，在電路板上製作混成型(hybrid)的雙閘極混頻器、二倍頻及次諧波混頻器，並測量其結果。

關鍵字

雙閘極場效電晶體混頻器 ； 倍頻器 ； 次諧波混頻器

並列摘要

In the wireless communication transceivers, the mixer plays an important role for the RF front end, especially in the dynamic range determination, and becomes the key components for the wireless industries. The thesis simulates & designs the sub-harmonic mixer used in the IEEE 802.11a standard via the CMOS process, taking the advantages of the easy integration with the baseband circuitries to accomplish the purpose of system-on-chip in the future.
The first part in the thesis discusses the key parameter in the receiver architecture, while the IC designs including the dual-gate mixer, the frequency doubler, and the sub-harmonic mixer are presented in the second port, using the TSMC 0.18um CMOS process with Agilent ADS circuit simulator.
The hybrid means for the above mixer circuits are also provided via discrete E-pHEMT devices with the measured result comparison.

並列關鍵字

Dual-gate FET Mixer ； Doubler ； Sub-harmonic Mixer

參考文獻

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