四階帶通積差調變器

A 4th-Order Bandpass Sigma-Delta Modulator

張家豪(Chia-Hau Chang)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2001年)

摘要

在本論文設計一個4 階帶通(Bandpass) Sigma-Delta 超取樣
(Oversampling)類比數位調變晶片，可用於無線通訊接收機架構中，
可以將類比數位轉換介面更接近天線端，以增加系統的可測性、單晶
片整合度與可以適應各種通訊系統，以符合數位無線通訊接收機的要
求，本調變器的設計是以全差動交換電容電路(Fully Differential
Switched Capacitor)的技術來達成，信號頻寬為200KHz 而中心頻率
為5MHz 此頻率為較常使用之中頻頻率,以達到65dB 之信號雜訊比
(SNR)，使用±2.5V 供應電壓，消耗功率為179.3mW 佈局面積為792um*1076um晶片面積為，晶片面積為1800um*1800um，使用的製程為UMC 0.5um 2p2m的CMOS 製程 。

關鍵字

帶通 ； 調變器 ； 交換電容電路 ； 類比數位轉換器

並列摘要

This paper presents a 4th-order bandpass sigma-delta oversampling modulator, which can be used in the digital wireless communication receiver. It converts analog signals to the digital domain at the intermediate frequency. The modulator is implemented in the UMC 0.5μm CMOS 2p2m process with power supply ±2.5V. The bandwidth is 200kHz centered at the 5Mhz.The sample frequency is 20MHz. The peak SNR is about 65 dB. The power consumption is 179.3mW. The modulator layout area is 792um*1076um. The chip area is 1800um*1800um。

並列關鍵字

bandpass ； sigma delta modulator ； switched-capacitor circuit ； analog digital conversion

參考文獻

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