適用於低功率之前饋式雙取樣四階帶通差和調變器

A DOUBLE-SAMPLED FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON FEEDFORWARD TOPOLOGY FOR LOW-POWER DESIGN

陳坤慶(Kun-Chiung Chen)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2005年)

摘要

摘要

這篇論文中，主要是設計一個GSM標準之80MHz前饋式四階帶通差和調變器。此調變器中所用的共振器僅使用一個運算放大器來實現，以降低功率消耗，再配合雙取樣的技術降低對運算放大器速度上的要求。另外，我們採用前饋式的架構以降低訊號在路徑上的失真而提高整體的訊噪比。整個調變器電路將使用TSMC 0.35μm 2P4M CMOS 製程來實現。在系統設計上，我們使用MATLAB 來模擬，希望能得到最大訊噪比80dB。而在供給電壓為3.3伏特下，功率消耗小於40mW。在電路設計上，我們使用HSPICE來模擬。其中所設計的運算放大器之直流增益為85dB、增益頻寬為361MHz。整個共振器是使用此運算放大器來完成，進而完成整個帶通調變器設計。模擬結果在訊號頻寬200kHz、取樣頻率40MHz (相當於80MHz)下，最大訊噪比為65dB (無image)，功率消耗42mW。

關鍵字

差和調變器

並列摘要

ABSTRACT

The design of an 80MHz fourth-order bandpass delta-sigma modulator with a double-delay, single-opamp resonator plus double sampling technique is proposed for GSM standard. The double-delay resonator uses only one opamp to reduce power dissipation, while double-sampling technique relaxes the performance requirement for the opamp. The circuit is based on the feedforward topology to reduce the distortion in the signal path. The circuit will be implemented in TSMC 0.35μm double-poly, four-metal CMOS process. Both behavioral-level and transistor-level simulation results are presented, and the circuit is expected to achieve 80dB peak SNR, and less than 40mW power consumption at 3.3V supply. According to HSPICE simulation, a peak SNR of 65dB is achieved for 200kHz signal bandwidth with sampling frequency of 40MHz (equivalent to 80MHz). The resonator is built using a high performance gain-boosted folded-cascade opamp. The opamp achieves 85dB of DC gain, 361 MHz GBW at 3.3V supply.

並列關鍵字

delta-sigma modulator

參考文獻

[2] D. A. Johns and K. Martin, Analog integrated circuit design, Wiley, 1997.

[3] D. Anastassiou, “Error Diffusion Coding for A/D Conversion,” IEEE Transactions on circuits and systems, Vo1.36, pp. 1175-1186, Sept. 1989.

[4] R. schreier, “An Empirical study of High order single-bit delta-sigma modulators,” IEEE Transactions on circuits and systems, Vo1.40, pp. 461-466, Aug. 1993.

[5] S. Lindfors, M. Länsirinne, and K. A. I.Halonen, “2.7V 50MHz IF sampling modulator with +37dBV IIP3,” Electron. Lett. vol. 37, pp. 150–151, Feb. 2001.

[6] A. Hairapetian, “An 81-MHz IF receiver in CMOS,” IEEE J. Solid-State Circuits,