2.4 GHz CMOS 低雜訊放大器及混波器之研製

Design and Implementation of 2.4GHz CMOS LNA and Mixer

何其穎(Chih-Ying Ho)

指導教授 ： 吳紹懋 博士

元智大學/工程學院/電機工程學系/碩士(2001年)

摘要

在本論文中，藉由台積電 0.35μm的CMOS製程完成了一階低雜訊放大器、二階低雜訊放大器和一個降頻混波器的設計與實現。一階的低雜訊放大器經過量測擁有2.78 dB的順向增益(Forward Gain)及4.2 dB 的雜訊指數(Noise Figure)。而二階的低雜訊放大器被設計為23.22 dB的順向增益及2.95 dB 的雜訊指數。降頻混波器是使用吉爾伯特式的架構來設計，它提供了2.63 dB的轉換增益(Conversion Gain)，其輸入三階交叉點(IIP3)為—5.86 dBm。

關鍵字

CMOS RF ； 低雜訊放大器 ； 混波器

並列摘要

In this thesis, a one-stage LNA, a two-stage LNA and a downconversion mixer have been designed and implemented with TSMC 0.35μm SPQM CMOS technology. A one-stage LNA with 2.78 dB forward gain and 4.2 dB noise figure is measured. Also designed are a two-stage LNA with a forward gain of 23.22 dB and a noise figure of 2.95 dB, and a downconversion mixer based on the Gilbert cell type with a conversion gain of 2.63 dB and an IIP3 of —5.86 dBm.

並列關鍵字

CMOS RF ； Low Noise Amplifier ； Mixer

參考文獻

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