3.1-10.6 GHz 超寬頻、24-GHz及 53-GHz CMOS 低雜訊放大器之設計與實現

Design and Implementation of 3.1-10.6 GHz UWB, 24-GHz, and 53-GHz CMOS Low Noise Amplifiers

楊弘鈺(Hung-Yu Yang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2008年)

https://doi.org/10.6837/NCNU.2008.00178

摘要

本論文以超寬頻(Ultra-wideband)低雜訊放大器、24-GHz及53-GHz CMOS 低雜訊放大器為研究目標，研究主題分成三部分：
第一部份為應用於接收機超寬頻系統之3.1~10.6 GHz低雜訊放大器。利用電流共用技術設計了三組低功率的CMOS低雜訊放大器，為了同時達到高且平坦的增益及較小的群延遲變化，在輸出級分別採用了串、並聯電感補償技術來增加主極點頻率，進而擴展3 dB頻寬。輸入級部份則使用電阻-電容負回授來達成匹配，並且有效的縮小電路面積。
首先，我們利用0.18 um CMOS製程設計了兩組低雜訊放大器，並分別使用不同感值的串聯補償電感來做探討。實驗結果顯示較低感值的低雜訊放大器在3.1~10.6 GHz頻率下有著最高增益S21為13.5 dB，輸入返回損耗低於-12 dB，輸出返回損耗低於-11.8 dB，以及平坦的雜訊指數3.61~4.68 dB，而較高感值的低雜訊放大器在3.1~10.6 GHz頻率下有著較平坦的增益S21為12.24±0.62dB，輸入、輸出返回損耗皆小於-8.5 dB，以及平坦的雜訊指數3.74~4.74 dB。為了達到更好的特性，第三組我們使用標準0.13 um CMOS 製程來實現此低雜訊放大器，實驗結果顯示此低雜訊放大器3-dB頻寬可達13 GHz，在頻段3.1~10.6 GHz，S21皆維持7.92±0.23 dB的增益，輸入、輸出返回損耗皆小於-14 dB，群延遲變化亦只有± 16.7 ps，而在10.5 GHz 有最低的2.5 dB雜訊指數，此電路消耗之功率為10.68 mW，非常適合應用在高解析度的脈波超寬頻系統。
第二部份為一可應用於汽車雷達系統的21~27 GHz超寬頻低雜訊放大器，利用台積電0.18 um CMOS 製程技術來實現。為了有足夠的增益，此低雜訊放大器由三級串接共源級放大器及一標準疊接放大器及所組成，在第二級和第三級採用了電流共用技術來降低電流的消耗，並加入電感補償技術來增加頻寬。實驗結果顯示此低雜訊放大器有8.5 GHz 的3-dB頻寬，在頻段21~27 GHz，S21皆維持9.3±1.3 dB的增益，輸入、輸出返回損耗皆小於-8.2 dB，雜訊指數為4.9~6.1 dB，及非常低的群延遲變化(± 8.1 ps)，非常適合應用於需要高解析度的雷達系統。
第三部份為一使用標準0.13 um CMOS 製程的低功率消耗53GHz (V-Band)低雜訊放大器。為了有足夠的增益，此低雜訊放大器由四級共源極串接放大器所組成。在第三級和第四級採用了電流共用技術來降低電流的消耗，而每一級的輸出負載均是利用電感及電容並聯諧振來使其操作頻率下有最大的增益。此次的低雜訊放大器量測結果電壓增益為14dB，輸入、輸出返回損耗皆小於-8.5 dB ，6.13dB的雜訊指數(NF)，和-20dBm的1dB功率輸入增益壓縮點及非常低的10.56mW功率消耗。

關鍵字

低雜訊放大器 ； 超寬頻低雜訊放大器 ； 24GHz低雜訊放大器 ； V-band ； 電流共用 ； 電感補償

並列摘要

This thesis aim is to design ultra wideband low noise amplifiers, 24-GHz and 53-GHz CMOS low noise amplifiers. Study the theme can be divided into three parts：
In first part, 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). The mainly three types of low noise amplifier were using current-sharing technique to achieve low-power consumption. In order to achieve not only high but also flat gain and small group-delay-variation at the same time, the series and shunt inductive peaking were adopted in the output stage to enhance the frequency of the dominant pole and then expand 3-dB bandwidth of the LNA. In the part of input stage, the R-C negative feedback can achieve impedance matching and reduce chip area.
First, we design two types of LNA in standard 0.18 um CMOS technology and use the difference gate inductor of series inductive peaking at the same time. The measured results of the first type LNA (lower gate inductor) show the maximum S21 of 13.5 dB, S11 below -12 dB, S22 below -11.8 dB and flat noise figure of 3.61~ 4.68 dB form 3.1 to 10.6 GHz. The measured results of the second type LNA (larger gate inductor) show the flatter S21 of 12.24±0.62 dB. The S11 and S22 below -8.5 dB and flat noise figure of 3.74 ~ 4.74 dB over 3.1-10.6 GHz while consuming 10.33 mW. In order to pursue better performances of the LNA, the third type of LNA is implemented in standard 0.13 um CMOS technology. The measured results show that the 3-dB bandwidth is 13 GHz, the power gain (S21) of 7.92±0.23 dB, input return loss (S11) and output return loss (S22) below -14 dB, and the group-delay-variation only ±16.7 ps over 3.1-10.6 GHz, minimum noise figure of 2.5 dB is achieved at 10.5 GHz while consuming 10.68 mW. The results show that the LNA is suitable for UWB pulse-radio system applications.
In the second part, 21~27 GHz low noise amplifier is implemented in standard TSMC 0.18 um CMOS technology and suitable for radar system. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages and a cascode amplifier. The current-sharing technique with inductive peaking is adopted for bandwidth enhancement in the second and third stage. The measured results show that the 3dB bandwidth is 8.5 GHz, the S21 of 9.3±1.3 dB, S11 and S22 below -8.2 dB, noise figure of 4.9~6.1 dB, and the very small group-delay-variation (±8.1 ps) over 21-27 GHz while consuming 27 mW.
The last part, low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 um CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and the fourth stage to reduce the power dissipation. The output of each stage is loaded with a LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (AV) of 14 dB with very low noise figure (NF) of 6.13 dB, and input referred 1-dB compression point (P1dB-in) of –20 dBm at 53 GHz. It consumed very small dc power of 10.56 mW.

並列關鍵字

low noise amplifier ； ultra wideband ； 24-GHz low noise amplifier ； V-band ； current-sharing ； inductive peaking

參考文獻

[1]B. Razavi, “RF Microelectronics,” Prentice-Hall, Inc., 1998.

[2]Q. Li, Y. P. Zhang, J. S. Chang, "An Inductorless Low-Noise Amplifier with Noise Cancellation for UWB Receiver Front-End, "IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 267-270, 2006.

[3]A. Bevilacqua, and A. M. Niknejad, "An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHz Wireless Receivers," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259-2268, Dec. 2004.

[4]Y. Park, C. H. Lee, J. D. Cressler, and J. Laskar, "Theoretical Analysis of a Low Dispersion SiGe LNA for Ultra-wideband Applications," IEEE Microwave and Wireless Components Letters, vol. 16, no. 9, pp. 517-519, Sept. 2006.

[5]C. C. Chen, Z. Y. Huang, C. C. Huang, N. K. Lu, "Time-constant Compensated LNA for Ultra-wideband Receiver," Proc. International Symposium on Intelligent Signal Processing and Communication Systems, pp. 13-16, 2005.