軟體無線電的架構已經把數位領域延升到中週頻率訊號處理的功能上了,例如頻帶選擇的濾波跟升頻降頻的變換。本論文中我們探討數位升頻器與數位降頻器的基本架構,並以降低運算量的前提,推導出更有效率的多通道數位升頻器與多通道數位降頻器,其中包含了兩個模組:移頻升取模組 (Frequency Shifting Interpolation Module)和移頻降取模組 (Frequency Shifting Decimation Module)。 然後以FPGA(Field Programmable Gate Array)的方式去設計並實現移頻升取模組與移頻降取模組,為了要避免浪費太多的邏輯閘,而把重點放在管線處理(Pipeline)FIR濾波器設計上。
The software radio architecture has extended the digital realm into the intermediate frequency (IF) signal processing functions, such as band-selective filtering and up/down frequency conversion. In this thesis, the fundamental architecture of digital up converter and digital down converter are discussed. A more efficient algorithm for the practical implementation of multi-channel digital up/down converter is deduced under the pre-requisite of a low computation load. The converter contains two modules including the Frequency Shifting Interpolation Module (FSI) and the Frequency Shifting Decimation Module (FSD). These modules are implemented using Field Programmable Gate Array (FPGA). In final, to significantly reduce the requirements of logic gates, the pipeline FIR filter is exploited.