軟體無線電架構下多模態數位中頻降頻器設計與實現

The Design and Implementation of Multi-mode Digital IF Downconverter for Software Defined Radio

藍柏澍(Bor-Shuh Lan)

指導教授 ： 鄭獻勳 ； 繆紹綱

中原大學/工學院/電子工程研究所/碩士(2002年)

https://doi.org/10.6840/cycu200200252

摘要

國際通訊聯盟(ITU)所制定之IMT-2000系統，其主要目標在於建立一個可全球漫遊、跨系統、跨網路的無縫隙之第三代行動通訊標準。而軟體定義無線電(Software Defined Radio)技術將傳統的硬體無線電平台轉換成更具彈性的軟體無線電平台，以支援多樣化之無線通訊標準。本論文以軟體無線電的概念，去實現適用於GSM、IS-95及W-CDMA系統之多模態數位中頻降頻器。

本論文所設計之高效率中頻處理架構，可透過參數化的設定達到多模態之應用。其中擁有高解析度的數值控制振盪器(Numerical Controlled Oscillator; NCO)，負責載波通道的選擇；高效率的CIC (Cascaded Integrator Comb)濾波器，提供寬範圍的升/降取率，達到窄頻和寬頻信號的擷取；而可程式規劃的FIR(Finite Impulse Response)濾波器，用以濾除頻帶外不需要的信號。此外本論文也針對有限位元長度之處理，進行定點運算模擬及評估，預測出數值截斷誤差(Truncation Error)、係數量化誤差(Quantization Error)、捨位誤差 (Round Off Error)及數值溢位誤差(Overflow Error)對系統所造成的影響，最後估算出符合系統需求之硬體架構。最後利用數位硬體描述語言VHDL，完成硬體的RTL設計，再利用Altera Max+plusII發展軟體作電路的合成(Logic Synthesis)、電路配置與繞線(Place & Route)以及時序驗證(Timing Verification)，完成多模態數位中頻降頻器之設計與實現。

關鍵字

數位中頻降頻器 ； VHDL ； 軟體定義無線電 ； 升/降取樣

並列摘要

The objective of the IMT-2000 system drawn up by ITU is to establish a seamless third generation mobile communication standard with the function of global roaming across any systems and networks. Software defined radio technique migrates the traditional hardware radio platforms to flexible software radio platforms that can support multiple air interface standards. In this thesis, we design a multi-mode digital IF downconverter for GSM、IS-95 and W-CDMA systems based on the concept of software defined radio.

In this thesis, we design an efficient IF processing architecture that can support multi-mode application via the download parameters. The high resolution Numerical Controlled Oscillator (NCO) allows carrier channels to be selected from a wide frequency band. The high efficient Cascaded Integrator Comb (CIC) filters with wide range interpolation /decimation rate can extract both desired narrowband and wideband signals. The programmable Finite Impulse Response (FIR) filter aims to reject the out of band signal. Furthermore, this thesis also uses fixed-point simulation to predict the errors caused by truncation, quantization, round-off and overflow for finite wordlength processing. Finally, we adopt hardware description language ‘VHDL’ for RTL design, and use Altera Max+PlusII development software to accomplish logic synthesis, circuit place & route and timing verification to complete the multi-mode digital IF downconverter design.

並列關鍵字

Software defined radio ； Interpolation / Decimation ； VHDL ； Digital IF Downconverter

參考文獻

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