以螺旋式電感為基礎的2.4GHz CMOS壓控振盪器及頻率合成器

Design and Chip Implementation of a Spiral Inductor Based 2.4GHz CMOS VCO and Frequency Synthesizer

張驥(Jie Chang)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2000年)

摘要

本篇論文所要介紹的是一種以螺旋式電感為基礎的2.4GHZ VCO及可工作在2.4GHz的CMOS鎖相迴路頻率合成器(2.4GHz CMOS PLL-based Frequency Synthesizer)之設計。它包含電壓控制振盪器(Voltage Controlled Oscillator)、相位—頻率偵測器(Phase—Frequency Detector)、電壓幫浦(Charge Pump)、迴路濾波器(Loop Filter)、前置除頻器(Precaler Divider)及多係數除頻器(Multi-Modulus Divider)。
電壓控制振盪器由控制電壓來調整振盪頻率，輸出頻率從2.38GHz到2.54GHz。相位—頻率偵測器比較輸入參考信號與除頻後的振盪器輸出的相位及頻率，輸出充電UP與放電DW的數位信號。電荷幫浦將相位—頻率偵測器的數位輸出訊號轉成電壓控制振盪器所能接受的類比訊號。迴路濾波器濾除高頻的雜訊。前置除頻器將振盪器的輸出處理到多係數除頻器所能接受的範圍，多係數除頻器從2400~2483。
這個頻率合成器是用TSMC 0.35 um 1P4M CMOS製程，此晶片面積含pad為1.1*1.22 mm2，輸出在2.4GHz時，功率消耗為45mW。

關鍵字

壓控振盪器 ； 頻率合成器 ； 鎖相迴路

並列摘要

A spiral inductor-based CMOS RFIC and 2.4GHz CMOS phase locked loop-based Frequency Synthesizer is presented. The synthesizer is implemented using a voltage controlled oscillator, phase—frequency detector, charge pump, loop filter, precaler divider and multi-modulus divider.
The frequency range of the VCO is from 2.38GHz to 2.54 GHz. The phase—frequency detector compares the reference signal’s phase and frequency with the feedback signal. It produces two digital signal UP and DW. The charge pump translates the digital signal of the phase—frequency detector to the analog signal that is accepted by the voltage controlled oscillator. The loop filter can eliminate the high frequency’s noise. The multi-modulus divider is composed of three divider.
The chip is implemented in TSMC 0.35um 1P4M CMOS process technology, and the chip area is 1.1*1.22mm2. The power dissipation is 45mW when the input frequency is 2.4GHz.

並列關鍵字

PLL ； VCO ； Synthesizer

參考文獻

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