應用於WLAN/WiMAX多頻段降頻器之研製

The Design and Implementation of a Multi-band Down-Converter for WLAN/WiMAX Applications

高稚淵(Chih-Yuan Kao)

指導教授 ： 楊正任

元智大學/電機通訊學院/通訊工程學系/碩士(2008年)

https://doi.org/10.6838/YZU.2008.00163

摘要

本論文之研究針對WLAN 802.11a/b/g(2.4/5.2GHz)與WiMAX 802.16d(3.5GHz)系統，設計ㄧ多頻段使用的降頻器，以低電壓操作、低功率損耗並同時減小晶片面積為目標。電路皆採全積體化方式，使用TSMC 0.18μm 1P6M CMOS製程技術製作完成。其中可同時共用多頻段低雜訊放大器採用shunt-peaking的架構，以減少元件的使用，經量測後在三個頻帶(2.4GHz/3.5GHz/5.2GHz)的增益分別為8.87 dB、10.40dB與8.41dB，雜訊指數分別為4.15dB、4.47dB、4.90dB，總消耗功率為13.4mW，包含pad之晶片總面積為0.76mm2。我們提出一修正後的Micro-mixer架構，除使用主動式負載改善了線性度，亦減少電阻的使用降低製程的偏移，在WiMAX 3.5GHz時之P1dB為-14.1dBm，IIP3為-3dBm。混頻器的核心功率消耗僅1.27mW，晶片面積為0.43mm2。具可切換之多頻帶壓控振盪器使用電容耦合的架構，可分別控制各頻段間的偏壓電流(2.393、3.457與5.085GHz)。相位雜訊分別為-119.2dBc/Hz@1MHz、-119.8dBc/Hz@1MHz與-118.2 dBc/Hz@1MHz，晶片面積僅約0.49mm2。

關鍵字

多頻段 ； 低雜訊放大器 ； 混頻器 ； 壓控振盪器

並列摘要

This thesis presents the implementation of a multi-band down-converter at WLAN 802.11a/b/g(2.4/5.2GHz) and WiMAX 802.16d(3.5GHz) systems. It’s aimed for low operating voltage、low power consumption and reducing area at the same chip. The circuits completed with fully integrated by TSMC 0.18μm 1P6M CMOS process. The concurrent multi-band LNA employs the shunt-peaking to reduce the number of components. The measured gain of this circuit are 8.87dB、10.40dB and 8.41dB at the frequency 2.4GHz、3.5GHz and 5.2GHz respectively. The measured NF of this circuit are 4.15dB、4.47dB and 4.90dB respectively. The total power consumption is 13.4mW, chip area included pad is 0.76mm2. We propose a modified construction of Micro-mixer to improve the linearity and reduce the number of resistor on the chip. The P1dB is -14.1dBm and the IIP3 is -3dBm at the frequency of 3.5GHz for WiMAX application. Besides, the power consumption of mixer-core is only 1.27mW, chip size is 0.43mm2. For switched multi-band VCO, we used capacitive coupling to control the bias current at different frequency band(2.393、3.457 and 5.085GHz). The corresponding phase noise are -119.2dBc/Hz@1MHz、-119.8dBc/Hz@ 1MHz and -118.2dBc/Hz@1MHz respectively. The chip size is 0.49mm2.

並列關鍵字

Multi-band ； LNA ； Mixer ； VCO

參考文獻

[9] Hsun Hsiang Chen, Kai Lin, “A Design for a Fully Integrated High-Gain LNA with 1.5dB-NF with 1.5dB-NF,” Journal of Da-Yeh University, Vol. 13, No.1, pp.41-49, 2004.

[7] Paul R.Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits,” Fourth Edition.

Loulou, “Dual Band CMOS LNA Design with Current Reuse

Nanoscale Technology, pp.57-61

Low-Noise Amplifiers and Receiver Architectures,” Sym. on VLSI