嵌壁式通道蕭特基位勢障電晶體之微縮探討

Study of Short Recessed Channel Schottky Barrier MOSFETs

夏瑞鍇(Ruei-Kai Shia)

指導教授 ： 施君興

元智大學/電機通訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6838/YZU.2011.00280

摘要

此論文探討嵌壁式通道蕭特基位勢障電晶體之電性行為及其微縮特性。嵌壁式通道架構應用於摻雜析離式蕭特基位勢障金氧半場效電晶體上，能有效地抑制短通道效應現象，並能同時提供一個較佳的開閉電流比值。而對嵌壁式通道之蕭特基位勢障電晶體而言，將摻雜析離層的引入蕭特基接面能提昇開閉電流比值，降低嵌壁式通道之架構所伴隨而來的寄生電阻問題。
嵌壁式通道之架構因其分段之通道，可以抑制汲極電壓作用在源極端之影響力，使得嵌壁式通道之電晶體在閘極長度微縮時能保持相同的元件特性。若以通道長度作為元件微縮的考量時，發現環狀佈植能改善嵌壁式通道摻雜析離蕭特基位勢障電晶體在微縮時較差的臨界電壓轉降。而為有效提高嵌壁式通道架構上之較差的導通電流，論文討論一種非對稱的嵌壁式通道架構來提供較好之導通電流，並且因環狀佈植對通道電位分布的影響，使元件對隨通道長度降低而產生的短通道效應有較佳的抑制能力。

關鍵字

嵌壁式通道 ； 摻雜析離層 ； 蕭特基位勢障 ； 環狀佈植

並列摘要

This thesis explores the current transport and device scaling of the recessed channel dopant segregated Schottky barrier MOSFETs (RC DS SBMOS). It also discusses an asymmetric source/drain structure of the RC DS SBMOS device to demonstrate a high on-current and suppress short-channel effect.
The use of the dopant segregation layer reduces the parasitic resistance, caused by the recessed channel, to have a higher on-current of the recessed channel Schottky barrier MOSFETs. The recessed channel structure has a separate source, channel and drain region. The separately isolated drain region relieves the penetration of drain-side electrical field to have a suppressed short-channel effect. A halo implant profile helps to improve the scalability of Schottky barrier MOSFETs further. The asymmetric drain recessed structure enhances the driving on-current, and simultaneously, minimizes the short-channel effect to have an optimized RC DS SBMOS device for the use in future CMOS applications.

並列關鍵字

Recessed channel ； Dopant Segregation Layer ； Schottky barrier ； Halo Implantation

參考文獻

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