針對結構化客製晶片 在擺置階段後的雙供應電壓最佳化

隨著積體電路(IC)的製程越來越先進，在設計IC時要處理的問題也越來越困難。一個晶片需要多層金屬層的光罩，而在製程進入90奈米之後，光罩的費用逾兩百萬美金。為了降低晶片的成本，但又希望不失效能，於是結構化客製晶片的技術在半導體產業推波助瀾下誕生。結構化客製晶片可以程式化部份的電路層，讓使用者可以分擔光罩的費用，來達成降低成本的目的。隨著科技的進步，單一晶片可容納的電晶體也大幅增加，而動態功率的消耗也因製程的進步而越來越多，許多降低功耗的方法中，雙供應電壓設計能夠有效減少功率的消耗。因此我們的研究結合結構化客製晶片與雙供應電壓設計，以創造出一個低成本且低功耗的晶片設計方法。在此篇論文中，在電路擺置後，我們能夠有效的利用在非關鍵路徑上邏輯閘本身的slack以不違反時序限制的前提下，將使用高電壓源的邏輯閘，轉換成使用低電壓源的邏輯閘，並在有低電壓源的邏輯閘驅動高電壓源邏輯閘之間插入電壓源轉換器，轉換電壓源。我們的實驗結果顯示，平均有77%的邏輯閘轉換成使用低電壓源的邏輯閘，而功率消耗也平均減少了49.75%。

關鍵字

雙供應電壓；結構化客製晶片

並列摘要

As semiconductor manufacturing technology advances, it is getting more difficult to deal with some design issues related to manufacturing. A design requires about 30 masks or so for a 90nm technology. Mask cost is more than US$ 2 million for a 90 nm technology. In order to reduce chip design and fabrication cost, structured ASIC technology is thus invented. Structured ASIC consists of some prefabricated layers and some predefined layers. It employs only a few layers such as via layers to implement a chip. As technology advances, a single chip can accommodate a significant number of transistors. Dynamic power consumption also increases significantly. Among the methods of reducing dynamic power consumption, dual supply voltage design is an effective one. Therefore, in this thesis, we develop a dual supply voltage assignment for algorithm a low-cost and low-power chip. Our algorithm can effectively assign more logic gates on non-critical paths that use lower supply voltage. This is done after placement. The algorithm can minimize the number of level converters inserted at the places where a high-voltage logic gate is driven by a low-voltage logic gate. Our experiments show that about 77% of logic gates are low-supply-voltage logic gates. Power consumption is on average reduced by 49.75% when compared to the designs that use only all high-voltage logic gates.

並列關鍵字

Dual Supply Voltage ； Structured ASICs

參考文獻

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針對結構化客製晶片在擺置階段後的雙供應電壓最佳化

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