低功率多輸出技術應用於掃描式的內建自我測試

由於大型積體電路(VLSI)製程的發展進步，功能需求的增加，故可在相同甚至更小面積的晶片上置入更多且更為複雜的設計，為了確保晶片在製造生產後的功能是完整且正確的，電路測試的問題也就越來越受到重視。而在晶片測試流程中，測試花費的時間、錯誤偵測覆蓋率(fault coverage)及功率消耗等都是一直被討論的重要議題，在本研究中除利用線性回饋移位暫存器(Linear Feed-back Shift Register)多輸出產生測試樣式的架構達到高錯誤覆蓋率及測試時間的減少，而在測試過程中過大的功率消耗產生可能會造成電路成本的增加及晶片良率的降低，所以我們更著重於減少在測試過程中產生的功率消耗(power consumption)。我們在線性回饋移位暫存器每一個新的掃描週期(scan cycle)開始時，選擇以輸出功率消耗較低的相容測試樣式做為輸出至掃描鏈的優先考量去送進待測電路(circuit under testing，CUT)，進而達到減少整體測試的功率消耗。經採用ISACS’89的測試電路進行實驗，經由實驗研究結果可以看到所提方法可有效的減少測試時的平均功率消耗約31%。

關鍵字

自我測試；線性回饋移位暫存器；低消耗功率

並列摘要

Today the VLSI can be put into more gates and has more complex design in the same space of chip. In order to ensure the chip is working and function correctly when manufacturing, it's very important for the circuit testing. During the circuit testing, the testing time, fault coverage and power consumption that all are the important issues be discussed and researched. In this paper, we presents a method to reduce the power consumption, this method based on the LFSR-based BIST ar-chitecture, besides utilize the multi-output approach of LFSR to reduce the testing time and remains the fault coverage, we more focus on how to reduce the power dissipation during the circuit testing. In each new scan cycle of LFSR, we select the test pattern which generated from the one output of LFSR and has the lowest switching activity, by way of reduce the number of switching activity to reduce the overall power consumption. In our experiment results on ISCAS’89 benchmark circuits, the results show our proposed method could reduce the test time and reduce the transition count to achieve power consumption improvement around 31%.

並列關鍵字

BIST ； LFSR ； Low power

參考文獻

[1] C.Dufaza, H.Viallon and C.Chevalier, “BIST hardware generator for mixed test scheme”, Proceedings of European Design and Test Conference, pp. 424-430, 1995.

[2] L. Li and Y. Min, “An efficient BIST design using LFSR-ROM architecture”, Proceedings of the Ninth Asian Test Symposium, pp. 386-390, Dec. 2000.

[3] G. Jervan, E. Orasson, H. Kruus and R. Ubar, “Hybrid BIST optimization using reseeding and test set compaction”, 10th Euromicro Conference on Digital System Design Architecture, Methods, and Tools, pp. 596-603, Aug. 2007.

[4] S. Neophytou, M. Michael and S. Tragoudas, “Efficient deterministic test genera-tion for BIST schemes with LFSR reseeding”, 12th IEEE International On-Line Testing Symposium, July 2006.

[5] A. Al-Yamani, S. Mitra and E. McCluskey, “BIST reseeding with very few seeds”, Proceedings of 21st VLSI Test Stmposium, pp. 69-74, May 2003.

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低功率多輸出技術應用於掃描式的內建自我測試

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