部份掃瞄設計的低功率測試方法

在本論文中，我們提供一種選擇正反器(DFF)的方法，使電路可在部份掃瞄設計下，進行轉態延遲障礙(transition delay fault, TDF)的測試。除了在測試時可有較低的功率消耗(Power dissipation)，並有較高的障礙涵蓋率(fault coverage)。此種方法係依據正反器輸出入端之可控制性(controllability)與可觀察性(observability)，挑選正反器加入掃描鍊。另外設計在測試過程中，將沒有加入掃描鍊的正反器用另一條時脈訊號來控制，達到freeze電路的能力。由ISCAS’89標準測試電路的實驗結果中可知，此種技術可以有效的降低在平移週期與抓取週期之平均功率與峰值功率，同時也提供了比全掃瞄鍊設計更高的LOC(Launch-On-Capture)轉態障礙涵蓋率與較低的硬體面積負擔。

關鍵字

部分掃描；延遲測試；低功率

並列摘要

In this thesis, we propose a method of selecting partial flip-flops for testing transition delay faults. As compared to full-scan design, this partial-scan method can achieve higher fault coverage and lower testing power. Scan flip-flops are selected based on controllability and observability of input signals and output gates of flip-flops. The non-scan flip-flops are controlled by another clock to freeze partial circuit during shift operation of scan testing. Experimental results on ISCAS89 benchmarks show that the proposed technique can reduce both average and peak power in shift and capture cycle than full-scan design. In addition, the method can also provide higher LOC transition fault coverage and utilize lower area overhead.

並列關鍵字

low power ； delay test ； partial scan

參考文獻

[1] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. of 11th IEEE VLSI Test Symp., pp. 4–9, 1993.

[2] S. Wang and S. K. Gupta, ”DS-LFSR: A New BIST TPG for Low Heat Dissipation,” in Proc. International Test Conference., pp. 848-857, 1997.

[3] P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82-92, May-June 2002.

[4] J. Saxena et al., “A Case Study of IR-drop in Structured At-Speed Testing”, in Proc. International Test Conference., pp. 1098 – 1104, 2003.

[6] Y.K. Malaiya and R. Narayansawamy, “Testing for timing faults in synchronous sequential circuits,” in Proc. International Test Conference., pp.560 –571, 1983.

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部份掃瞄設計的低功率測試方法

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