使用部分封阻閘之低功率部分掃瞄測試設計

Low-Power Partial-Scan Test with Partial Gating

陸慶恩(Cing-En Li)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2010年)

https://doi.org/10.6840/CYCU.2010.00561

摘要

數位電路使用掃瞄串可以增加電路可測性，加入封阻閘可以降低測試功率，但掃瞄串及封阻閘皆會降低電路效能及速度，為解決此問題，我們研究如何使用部分掃瞄及部分封阻閘，進行電路之低功率測試設計。為了減少對電路速度的影響，我們避免將關鍵路徑上的正反器加入掃瞄串，如此產生之部分掃瞄電路，其中未加入掃瞄串的正反器，在測試過程將使用另一個時脈信號控制，如此可在位移掃瞄串之測試資料時，獨立凍結未加入掃瞄正反器，以降低測試時之位移功率。由於位移測試資料時，電路內部並不需要隨之產生信號變化，產生多餘之功率消耗，因此可以在掃瞄正反器輸出加入封阻閘，阻止正反器變化的信號傳至內部電路，但封阻閘亦會影響電路效能及速度，設計時並不需要在所有掃瞄正反器加上封阻閘，因此我們亦研究尋找部分的掃瞄正反器，將其輸出加入封阻閘，即可達到低功率測試。為了選擇正反器加入封阻閘，我們提出一種新的方法，只觀察正反器輸出所接之第一層邏輯閘數量，以及這些邏輯閘其他輸入之可控制性，用以決定掃瞄正反器加入封阻閘的優先順序，以及較適合的封阻閘類型。我們採用ISCAS89標準測試電路，實驗所設計的方法，包括加入各種比例的封阻閘，分析可以降低之測試功率比例，也分別觀察測試時之平均功率及峰值功率。與現有文獻[9]比較，當加入50%封阻閘時，我們的方法，可以在功率下降比例方面比文獻[9]多14.62%；當加入80%的封阻閘時，功率下降比例則比文獻[9]多了27.31%。

關鍵字

部份掃瞄串 ； 轉態延遲錯誤 ； 封阻閘 ； 低測試功率

並列摘要

For digital circuits, scan design can improve testability and block gates can help reduce testing power. However, these two methods may affect the efficiency and operation speed of circuits. To solve this problem, we study on utilizing partial scan and partial gating for low-power testing design. For the operation efficiency of circuits, we choose the flip-flops on critical paths to be non-scan flip-flops. For the obtained partial-scan circuits, we use a separate clock for controlling non-scan flip-flops. During the shift operation of scan test, we can freeze non-scan flip-flops to reduce power consumption. In addition, we need not to send signals into combinational part of circuits during the shift operation. Therefore we can add block gates at the output ports of scan flip-flops to prevent sending signal transitions into combinational part. This can also help reduce test power, but may affect the operation efficiency of circuits as scan flip-flops. Consequently, we also study a method to select a part of scan flip-flops for adding block gates. Our method takes into account the fanout numbers of scan flip-flops and the first-level fanout logic gates. For these gates, the controllability values of other inputs are considered for later calculation. The fanout numbers of scan flip-flops are more important in the calculation for choosing flip-flops for adding block gates. The types of block gates are also decided in the process. We experiment our method on ISCAS89 benchmark circuits for verification. The results include analysis on reduction effect for various percentage of adding block gates. We also analyze the effect on average power and peak power in the experiments. In comparison with the previous paper [9], our method provides a test procedure with 14.62% more power reduction than [9] when adding 50% of block cells. When adding 80% of block cells, our test procedure can achieve 27.31% more power reduction.

並列關鍵字

partial scan ； transition faults ； gating cell ； low-power testing

參考文獻

[1] P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, 2002, pp. 80-90.

[2] S. Ravi, "Power-aware Test: Challenges and Solutions," in Proc. Int. Test Conf., Oct. 2007, Lecture 2.2, Page(s):1-10.

[3] HUANG, T. and LEE, K. 2001. “Reduction of power consumption in scan-based circuits during test application by an input control technique”, IEEE Trans on Computer Aided Design of Integrated Circuits and System, Vol.20,No 7,July 2001, 911–917.

[4] S. Gerstendorfer and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," in Proc. Int. Test Conf., Sep. 1999, Paper 4.1, pp. 77-84.

[5] A. Hertwig and H.-J. Wunderlich, “Low Power Serial Built-In Self-Test,” Proc. European Test Workshop, 1998, pp. 49-53.