全二維穿隧電晶體與非揮發性記憶體之研究

The Study of All 2D Tunneling Field Effect Transistors and Non-Volatile Memories

楊士賢(Shih-Hsien Yang)

指導教授 ： 連振炘 ； 林彥甫

國立清華大學/電機資訊學院/電子工程研究所/博士(2019年)

摘要

隨著摩爾定律推進下，每兩年電晶體數量將會倍增，至今電晶體特徵長度為5奈米，已經不到50個矽原子長度，未來電晶體微縮已越來越困難，除了更激進地縮小電晶體外，選擇其他非傳統矽材料結構電晶體以及尋找其他應用上的改進成為後摩爾時代的兩個選擇方向，而本文將在後摩爾時代的時空背景下，尋求二維材料在更改傳統電晶體型式的低功耗電晶體與多功能應用上將可能扮演的角色。
在現代積體電路中，隨著電晶體封裝密度的增加，功耗成爲一個關鍵問題。穿隧場效電晶體具有帶間穿隧特性，被認爲是一種可替代傳統電晶體的電子結構，以減少電晶體關閉時的能量損失，並可在室溫下實現快速的電晶體開關。最近，在VdW HS(hetero-structures, HS)中的半導體材料，證實了能帶對能帶的穿隧行爲。形成能帶對能帶的穿隧原因是在異質介面附近發生了明顯的能帶彎曲，導致載子積累。在本工作中，爲了研究第三型(type-III)電晶體中的電荷傳輸，我們採用相同的能帶彎曲概念來製造凡得瓦黑磷(BP)/二硫化鉬(MoS2)HS。通過分析其電性能的溫度依賴性，我們仔細地排除了金屬-半導體接觸電阻的貢獻，提高了我們對二維第三型電晶體中載子注入的理解。BP/MoS2 HS表現出負微分電阻(NDR)和逆向偏壓下大的穿隧電流，有力地提供了能帶對能帶的穿隧證據。最後，我們還設計了一種基於離子液體閘極HS的電晶體，該電晶體證明了SS可以成功地克服60 mV/dec.的物理極限(達到42 mV/dec.)。這項工作提高了我們對分層HS中電荷傳輸的理解，並有助於提高下一代奈米電子產品的能源效率。
隨著物聯網(IoT)概念的蓬勃發展，多功能整合在一個元件的設計，在節約成本、設備小型化、節能等方面受到越來越多的關注。自石墨烯(Graphene, Gr)首次報導以來，二維材料因其獨特的原子層結構和凡得瓦相互作用，被認為是未來電子應用的候選材料。在這裡，我們演示了一個全二維二硒化錸(ReSe2)/氮化錋(hBN)/石墨烯(Gr) HS通過垂直耦合一個ReSe2場效電晶體和一個電荷儲存元件。這種獨特的HS依靠凡得瓦力垂直堆疊的新穎結構，可以實現優良的非揮發性記憶體、光電憶阻器以及可程式化處裡的訊號處理電路。ReSe2/hBN/Gr HS的記憶體在寫入與抹除電流比(> 105)和相當長的持久性(>10,000秒)內提供了優異記憶體性能和連續可調記憶體狀態。此外，全二維HS設計使得光可以穿透Gr接觸層，到達光敏感度高的ReSe2通道，從而使其具有低功耗的全可見光譜光電記憶體功能。更有趣的是，由於ReSe2具有雙極導電特性，ReSe2/hBN/Gr HS可以實現一個多功能的光可程式化的訊號處理電路，可用於反向器和倍頻器的應用上。最後，我們進一步提出了無消耗功耗的ReSe2/hBN/Gr HS影像儲存器的概念，簡化了典型的相機成像儲存系統，揭示了全二維HS電子在當今光電可程式化處理電路與光電資訊儲存系統領域的潛在應用。

關鍵字

二維材料 ； 二硫化鉬 ； 光偵測器 ； 二硒化錸 ； 穿隧電晶體 ； 非揮發性記憶體

並列摘要

According Moore's law, the number of transistors will double every two years, so far the characteristic length in transistor is 5 nm, which is less than 50 silicon atoms, future scaling in transistors has been more and more difficult. In addition to the scalling of transistors, choose other transistors with non-traditional structures and look for other improvements in applications as two options for the post-moore era. In this article, we explore the opportunities of 2D materials in low power transistors and multifunctional applications in the post-moore era.
In modern integrated circuits, power consumption becomes a key problem with the increase of transistor package density.Tunneling field effect transistors(TEETs) have the characteristics of inter-band tunneling, which is considered as an electronic structure that can replace the traditional transistors to reduce the energy loss when the transistors turn off, and can realize the fast switching of transistors at room temperature. Recently, semiconductor material from van der Waals (VdW) hetero-structures (HS) demonstrated band-to-band tunneling (BTBT). The formation of BTBT is due to the apparent band bending near the heterogeneous interface, leading to carrier accumulation. In this work, in order to study the charge transfer in type-III transistors, we use the same concept of band bending to produce VdW black phosphorus (BP)/ MoS2 HS. By analyzing the temperature dependence of its electrical properties, we carefully excluded the contribution of metal-semiconductor contact resistance and improved our understanding of carrier injection in 2D type-III transistors. BP/MoS2 HS exhibit negative differential resistance (NDR) and large tunneling current at reverse bias, providing strong evidence of BTBT. Finally, we design a transistor based on ionic liquid gate HS, which proves that the subthreshold swing (SS) can successfully overcome the physical limit of 60 mV/dec. (achieve 42 mV/dec.). This work improves our understanding of charge transfer in layered HS and contributes to the energy efficiency of next-generation nanoelectronics.
With the rapid development of the Internet of things (IoT) concept, multifunction integration in the design of a component has attracted more and more attention in cost saving, device miniaturization, energy saving and other aspects. Since Graphene (Gr) was first reported, two-dimensional materials are considered as candidate materials for future electronic applications due to their unique atomic layer structure and VdW interaction. Here, we demonstrated a 2D ReSe2/hBN/Gr HS through a vertical coupling a ReSe2 field-effect transistor and a Gr layer charge storage element. This unique HS relies on a novel vertical-stacked VdW structure to achieve excellent non-volatile memory, photo-detector, and light programmable signal processing circuits. The memory of ReSe2/hBN/Gr HS provides excellent memory performance and continuously adjustable memory state in the write and erase current ratio (ON/OFF ratio > 105) and considerable retention (>10,000 seconds). In addition, the full 2D HS design enables light to penetrate the contact layer of Gr and reach the ReSe2 channel, so that it has the function of fully visible spectral photoelectric memory with low power consumption. More interestingly, ReSe2/hBN/Gr HS can implement a multifunctional optical programmable signal processing circuit for inverters and frequency doubler applications due to its ambipolar conductivity. Finally, we further propose the concept of power-free ReSe2/hBN/Gr HS image storage, which simplifies the typical camera imaging storage system, and reveals the potential applications of 2D HS electronics in the fields of optoelectronic programmable processing circuits and image storage systems.

並列關鍵字

2D materials ； MoS2 ； ReSe2 ； TFET ； memory ； sensor

參考文獻

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