28奈米級互補金屬氧化物半導體元件在鈦化氮/二氧化鉿/二氧化矽的堆疊式閘極中的可靠度影響

Impact of TiN/HfO2/SiO2 Gate Stack Reliabilities for 28nm Node CMOS Devices

黃大正(Da-Cheng Huang)

指導教授 ： 龔正 ； 黃智方

國立清華大學/電機資訊學院/電子工程研究所/博士(2015年)

摘要

在MOSFET的超薄介電層以矽製成的微電子元件時代的關鍵元件，所述二氧化矽閘極氧化物到了設備的性能和縮放的關鍵。以SiO2為基礎的閘極氧化物的物理厚度接近〜2奈米，一些關鍵的電介質參數退化：閘極漏電流，多晶矽閘極氧化層擊穿，和通道遷移率。解決的辦法是與具有更高介電常數（高k）的材料代替傳統的二氧化矽閘極氧化物。高k值絕緣體可以生長為相同的（或更薄）等效電氧化層厚度（EOT）物理上更厚，從而提供顯著閘極漏電流減少。高k材料被推出，取代SiO2，來解決閘極漏電問題。即使相當大的性能改進和閘極漏電減少已經實現，高κ材質元件帶來新的元件可靠度挑戰，例如正和負偏壓溫度不穩定性（P / NBTI）和熱載流子注入（HCI）需要進行研究。 本文提出一種實現在堆疊式TiN /HfO2 /SiO2的新型28奈米CMOS邏輯高k /金屬閘（HK / MG）技術的可靠性影響。在第2章中，運用快速運作的量測技術在高k電介質中，以減少由於電荷被捕獲/脫逃。第3章提出P / NBTI和HCI在先進HK / MG介質CMOSFET之間退化特性的相關性研究。一種可靠性的最佳化製程研究，像是氧的敏感度和閘極疊層的厚度效果將在第4章進行討論。在第5章，針對隨機電報式訊號RTS幅度分佈之電流波動，通過統計分析和使用RTS來估算元件壽命。在第6章呈獻交流式高溫壽命AC HTOL 測試和目前的各種元件退化機制，如NBTI，PBTI和HCI在6T型（6個電晶體型）靜態隨機存取記憶體(SRAM)的研究。且探討了氮化退火（PNA）可改進PBTI的可靠性，最後，第7章是結論。

關鍵字

高介電 ； 元件 ； CMOSFET ； PBTI ； NBTI ； Reliability

並列摘要

The ultra-thin gate dielectrics in MOSFETs remain the key element in conventional silicon-based microelectronic devices era, the SiO2 gate oxide has played a critical role in device performance and scaling. As the physical thickness of SiO2-based gate oxides approaches ~2 nm, some key dielectric parameters degrade: gate leakage current, oxide breakdown from the poly-silicon gate electrode, and channel mobility. The solution is to replace conventional SiO2 gate oxides with a material having higher permittivity (high-k). High-k insulators can be grown physically thicker for the same (or thinner) equivalent electrical oxide thickness (EOT), thus offering significant gate leakage reduction. High-k material is introduced to replace SiO2 to solve the gate leakage problem. Even though considerable performance improvement and gate leakage reduction have been achieved, new reliability challenges of high-κ devices such as the positive and negative bias temperature instability (P/NBTI) and hot carrier injection (HCI) need to be investigated.
This dissertation presents an impact of reliability on a novel 28 nm CMOS logic high-k/metal-gate (HK/MG) technologies realized by stacking TiN/HfO2/SiO2. The fast transient measurement technique to reduce the post-stress transient effect due to charge trapping/detrapping in high-k dielectric is demonstrated in Chapter 2. The correlation of degradation characteristics between the P/NBTI and HCI in advanced HK/MG dielectric CMOSFET is proposed in Chapter 3. Oxygen sensitivity and the thickness effect for the optimized gate stack is discussed in Chapter 4. Chapter 5 focuses on current fluctuations in HK gate dielectric MOSFETs due to RTS amplitude distribution, the carrier lifetime estimated with RTS by using graphical extrapolation is discussed. An overview of various aging mechanisms such as NBTI, PBTI, and HCI in the 6T SRAM by AC HTOL stress is presented in Chapter 6, and a post nitridation anneal (PNA) treatment that improves the PBTI reliability is also presented in Chapter 6. Finally, conclusions are made in Chapter 7.

並列關鍵字

high-k ； device ； 互補式金氧半電晶體 ； 正偏壓溫度不穩定性 ； 負偏壓溫度不穩定性 ； 可靠度

參考文獻

Chapter 1

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[1.4] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, ‘‘Application of HfSiON as a Gate Dielectric Material,’’ Appl. Phys. Lett. Vol. 80, p. 3183, 2002.

[1.5] E. P. Gusev, C. Cabral, M. Copel, C. D’Emic, and M. Gribelyuk, ‘‘Ultrathin HfO2 Films Grown on Silicon by Atomic Layer Deposition for Advanced Gate Dielectrics Applications,’’ Microelectron. Eng., Vol. 69, p. 145, 2003.