一個使用連續逼近暫存以及增量型三角積分轉換器的低功耗混合式類比數位轉換器

本論文提出一個低電壓操作，且高能源效率的混合式類比數位轉換器(ADC)，應用於儀器量測校準與生醫的領域上。基於混和式ADC的架構與技巧，在系統上我們分別在前端使用了六位元解析度的連續逼近暫存類比數位轉換器(SAR ADC)，以及在後端使用了增量形三角積分轉換器(Incremental Sigma-Delta Modulator)，進一步達到了整體所預計的解析度。為了降低整體電路的功耗，我們針對前端SAR ADC的電容切法做了改善與創新，成功降低了所需的switching energy。而在後端的Incremental Sigma-Delta Modulator，使用了切換式運算放大器技術來解決小於一伏特低電壓下MOS開關無法傳遞訊號之問題，也藉由Cascade-of-Integrators Feed-forward (CIFF) 架構將輸入訊號直接向前傳遞至量化器輸入端使得各級積分器內的訊號擺幅減小，藉此減少在低電壓下運算放大器的規格要求。再者，SAR ADC中的電容陣列是以unary的方式做實現，意即每個電容都是單位電容，再配合上Dynamic Element Matching(DEM)，將存在電容陣列上的誤差打散，得到更好的線性度，進一步達到系統所需的規格。此架構使用TN90GUTM 1P9M 互補式金氧半導體製程製作，晶片面積為0.301mm2。在512-kHz的取樣頻率以及0.5-ms的conversion time下，達到了整體92.66-dB的SNDR，並且在500-mV的操作電壓下消耗了5.481μW，等效所得到的figure of merit(FoM) 為175.93-dB，和其他的成果相比較也是具有競爭力的。

關鍵字

連續逼近暫存；增量型；三角積分；低功耗；類比數位轉換器

並列摘要

This Thesis presents a low-voltage operation and high energy efficient hybrid analog-to-digital converter (ADC) for instrumentation or biomedical systems applications. It is based on an energy-efficient hybrid ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine incremental ΔΣ conversion, to achieve target resolution performance. The proposed ADC operates at ultra-low supply voltage, 0.5V, to save power consumption. Novel switching technique in coarse SAR ADC is utilized to improve the power efficiency of the ADC in low voltage operation. In fine incremental ΔΣ modulator, switched-op amp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of integrators feed-forward (CIFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. Furthermore, SAR ADC comprises a 6 bit unary-weighted capacitor DAC array, which means every capacitor in the DAC array is equal to unit capacitor. Dynamic element matching (DEM) is used to average the mismatch and error on capacitor DAC array, hence achieve both low offset and high linearity. The proposed ADC is fabricated in TN90GUTM technology, achieving a 92.66-dB SNDR at 512-kHz sampling rate and 0.5-ms conversion time. The proposed ADC occupies core area of 0.301-mm2 and dissipates only 5.481-μW from a 500-mV power supply. The figure of merit (FoM) of overall ADC is 175.93-dB, which is competitive to state-of-the-art designs.

並列關鍵字

SAR ； Incremental ； Delta Sigma ； Low Power ； Analog Digital Converter

參考文獻

[1] J. Goes, N. Paulino, H. Pinto, R. Monteiro, B. Vaz, and A. S. Garcao, “Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12, pp. 2595- 2604, Dec. 2005.

[2] J. Johansson, H. Neubauer, and H. Hauer, “A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications,” in Proc. Eur. Solid-State Circuit Conf., pp. 161-164, Sept. 2003.

[5] F. Cannillo, E. Prefasi, L. Hernandez, E. Pun, F. Yazicioglu, and C. V. Hoof, “1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. Eur. Solid-State Circuit Conf., pp. 267-270, Sept. 2011.

[6] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585-1593, July 2012.

[7] Youngcheol Chae; Souri, K.; Makinwa, K.A.A., "A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset," in Solid-State Circuits, IEEE Journal of , vol.48, no.12, pp.3019-3027, Dec. 2013

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一個使用連續逼近暫存以及增量型三角積分轉換器的低功耗混合式類比數位轉換器

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