Adaptable Noisy Transistors for Stochastic Neuromorphic Computation in VLSI

雜訊可調變電晶體以應用於隨機仿神經積體電路運算

邱當榮(Tang-Jung Chiu)

指導教授 ： 陳新

國立清華大學/電機資訊學院/電子工程研究所/博士(2011年)

摘要

Neurons encode and transmit information as the changes of their membrane potentials, which exhibit non-negligible low-frequency noise. One major noise source is attributed to the random opening and closing of ion channels, and the noise spectrum has the 1/f feature also observed in the transistor noise. More interestingly, the noise is found to play a beneficial rather than harmful role for neural computation. As the transistor noise increases dramatically for the CMOS nano-technology, stochastic neuromorphic circuits able to use noise for computation like biological neurons have thus been attractive.
This thesis presents three field-effect transistors (FETs) to generate and adapt the low- frequency noise in VLSI power-efficiently, which are named as the shallow-trench- isolation (STI) FET, the octagonal dual-gate FET (ODGFET), and the resist- protection-oxide (RPO) FET. The gate and the drain of the STI-FET are used to adapt the noise induced by the STI-silicon interface traps. The ODGFET is a direct extension of the STI-FET, whose dual-gate structure is to separately control the DC and noise characteristics. The RPO traps enhance greatly the low-frequency noise of the RPO-FET, whose noise level is further adaptable by the drain voltage. The trapping and de-trapping of carriers in the three transistors thus correspond to the random opening and closing of ion channels in a neuron.
This thesis then proposes an equivalent circuit model, named as the conductance- inductance (GL) network model, to transform the transistors’ low-frequency noise from the frequency domain to the time domain, facilitating transient simulation of the low-frequency noise of the three adaptable noisy transistors in SPICE. Finally, several testing circuits are designed for the three transistors to further validate their ability to adapt and to enhance the low-frequency noise at the circuit level.
All the proposed transistors and their corresponding testing circuits are fabricated with the TSMC standard 0.18-μm CMOS logic technology. No additional masks or process steps are required, facilitating the development of stochastic neuromorphic computation with oridinary CMOS integrated circuits.

關鍵字

仿神經 ； 低頻雜訊 ； 元件設計

並列摘要

神經細胞藉由改變其自身的細胞膜電位，來做神經訊號的編碼和傳遞，而過程中會隨之產生大量的低頻雜訊。此低頻雜訊主要源自離子通道的隨機開闔現象：離子通道廣泛存在於神經細胞的細胞膜上，神經細胞藉由控制離子通道的開啟與關閉，來控制離子進出神經細胞的時機與數目；而離子通道隨機性的開或關所造成的低頻雜訊頻譜，非常類似於電晶體產生低頻雜訊的機制。更有趣的是，神經科學家研究發現，此一低頻雜訊不僅不會對神經元的運算造成傷害，其實更有助於神經元進行更穩健的訊號處理。隨著半導體製程的演進，電晶體尺寸得以不斷微縮，但其低頻雜訊卻也不斷增強，而損害傳統積體電路的訊號處理的精確性。反觀隨機仿神經積體電路，能夠利用調變雜訊來進行更穩健的訊號處理，因此，此一仿生設計理念逐漸受到重視。
本論文首先發展三種電晶體結構，來加大其自身的低頻雜訊；並且此低頻雜訊的擾動振幅大小，可藉由外加偏壓來調變。第一種命名為淺溝槽隔離電晶體，其低頻雜訊增強的物理機制源於淺溝槽隔離氧化層介面具有較多的鍵結缺陷；而其雜訊的振幅大小，可以進一步藉由調變其閘極或汲極偏壓來控制。第二種命名為八角形雙閘極電晶體，其結構直接延伸自淺溝槽隔離電晶體，而雙閘極的設計理念是用以分開控制電晶體的直流特性與低頻雜訊特性。第三種命名為電阻保護氧化層電晶體，其低頻雜訊增強的物理機制源於電阻保護氧化層介面具有較多的鍵結缺陷，而其低頻雜訊的大小更可進一步藉由汲極偏壓來調變。這三種電晶體對通道載子的隨機捕獲機制，便可類比於神經細胞對離子通道的隨機開闔現象。
本論文接著發展電晶體低頻雜訊的時域等效電路模型，並將之命名為電導-電感網路模型。此一模型用以將電晶體的低頻雜訊由頻域等效轉換至時域，使電晶體雜訊能夠使用SPICE進行暫態模擬分析。最後，本論文亦分別針對上述三種雜訊可調變電晶體，設計其相對應的測試電路，藉以在電路層級上再驗證一次，這些電晶體在雜訊增強與雜訊可調變上的能力。
上述所有的電晶體結構與它們相對應的測試電路，全部使用台積電0.18微米標準金氧半邏輯製程，完全不需額外光罩或製程調整。因此完全相容於傳統的金氧半積體電路設計，進而簡化了隨機仿神經積體電路的設計難度。

並列關鍵字

Neuromorphic ； Low-frequency noise ； Device design

參考文獻

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