可調變式倒傳遞類神經網路處理器晶片設計

The Chip Design of Reconfigurable Back Propagation Neural Network Processor

郭天川(Tian-Chuan Kuo)

指導教授 ： 吳俊德

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

https://doi.org/10.6837/NCNU.2009.00054

摘要

本篇論文提出一顆具有可調變式倒傳遞類神經網路處理器硬體架構，以及做非線性函數的近似。調變的目的是使網路更具彈性，以方便用於各種不同的應用。把類神經網路的結構寫成指令形式，然後經由輸入/輸出埠(I/O)寫入晶片裡，來調變類神經網路的架構及組態。在執行網路運算我們提出多處理器運算架構，使用此架構達成平行運算能力，以減少倒傳遞類神經網路在做學習循環時所消耗的時間。最後，晶片應用UMC 90 nm 標準單元(standard cell)合成出處理器電路，處理器晶片面積約為2.2x2.2 ，工作頻率為50MHz。

關鍵字

可調變 ； 倒傳遞類神經網路 ； 多處理器

並列摘要

This paper presents a reconfigurable back-propagation neural network (BPNN) processor hardware architecture as well as doing non-linear function approximation. The purpose of modulation is to make the network more flexible for different applications. The neural network architecture is written in the from of instructions into the chip through the input / output ports (I / O) to reconfigure the neural network architecture. In the implementation of Network Computing, the multi-processor computing architecture is applied in order to reach the parallel computing capacity, and to reduce the time consumed for the learning cycle of back-propagation neural network. The BPNN chip is synthesized by UMC 90nm cell library, and is worked at 50 MHz. The area of the BPNN chip is about 2.2x2.2 mm2 .

並列關鍵字

back-propagation neural network ； reconfigurable ； multi-processor

參考文獻

Bibliography

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