Booster Circuit to Reduce Long Interconnect Delay

楊孟蓉(Meng-Rong Yang)

指導教授 ： 張彌彰

國立清華大學/電機資訊學院/電子工程研究所/碩士(2009年)

摘要

As VLSI technologies continue to scale, interconnects critically limit overall chip performance and power constraints.
In this thesis, booster insertion is chosen for a lossy, thin and long interconnect line. A booster circuit is used for reducing interconnect delay and power consumption, while occupying a smaller area than repeater insertion mythology. The booster circuit detects a transition earlier than a standard repeater and amplifies it to a full swing level.
Two booster circuit models are built for easily predicting booster characteristics, and a comparison of two booster models and circuit simulations is demonstrated. And placement sensitivity and crosstalk effect of the booster circuit are explored in the thesis. Performance comparison between booster insertion and conventional inverter insertion is also presented. All booster circuits are simulated with TSMC 0.35 um CMOS technology.

關鍵字

interconnect ； repeater insertion

參考文獻

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