高速除頻器之設計與基底雜訊對其電路特性影響之研究

High Speed Frequency Divider Design and the Substrate Noise Coupling on Circuit Characteristics

李侑紘(You-Hung Lee)

指導教授 ： 徐碩鴻

國立清華大學/電機資訊學院/電子工程研究所/碩士(2007年)

摘要

無資料

關鍵字

除頻器 ； 基底雜訊

並列摘要

無資料

並列關鍵字

Frequency Divider ； Substrate Noise

參考文獻

[1] H. R. Rategh, H. Samavati, and Thomas H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, vol. 35, issue 5, pp. 780 – 787, May 2000.

[2] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813–821, June 1999.

[3] H. R. Rategh and T. H. Lee, “Superharmonic injection locked oscillators as low power frequency dividers,” in Symp. VLSI Circuits Dig., pp. 132–135, 1998.

[4] A. Mirzaei, “Transient analysis of injection-locked frequency dividers,” IEEE Circuits and Systems, vol. 3, pp. III-381 - III-384, Aug. 2002.

[5] A. Nordbotten, “LMSD Systems and their Application,”IEEE Communications Magazine, vol. 38, Issue 6, pp. 150 – 154, June 2000.