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  • 學位論文

新型三維堆疊封裝結構之設計與可靠度評估

Design and Reliability Assessment of Novel 3D IC Packaging

指導教授 : 江國寧
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摘要


近年來,由於黃光微影製程遭受到物理限制,使得元件的最小線寬無法無止境的縮小,微電子工業已面臨到難以追隨摩爾定律(Moore’s law)的瓶頸。然而,為了使電子產品能夠滿足輕、薄、短、小的需求,研究方向已逐漸轉往新摩爾定律(more than Moore’s law)的系統級封裝(system-in-package, SiP)發展。系統級封裝結構主要是藉由直通矽晶穿孔(through silicon via, TSV)或覆晶(flip-chip)等方式,透過晶片堆疊或並排達到整合的目的,此舉可避免元件線寬阻擋電子元件之發展。在本研究中,將提出一使用內埋式晶圓級封裝且具雙面電訊接點與堆疊晶片之結構。此結構之扇出(fan-out)的特性可解決晶片與印刷電路板墊片間距不一致的連接問題。 首先,以有限單元法探討此結構之散熱特性,同時也與傳統晶圓級封裝結構之散熱行為進行比較。由於本研究所提出之結構其面積較大且具有熱傳特性佳之矽載板,可提供另一散熱途徑進行散熱,有效降低封裝結構之接面熱阻至39 °C/W,而傳統晶圓級封裝結構之熱阻為49 °C/W,此結構可大大提升電子封裝的散熱能力。根據雙面電訊接點且雙晶片堆疊結構在熱循環負載中之熱機械行為,對於錫球、重新佈線層之整體可靠度評估可藉由有限單元法進行研究。使用較軟的應力緩衝材料並搭配熱膨脹係數與印刷電路板接近的載板,可使錫球的壽命高於1,000循環。而基於本研究提出的設計準則,本研究提出之封裝結構可成功應用在大尺寸晶片之封裝上,並得到封裝產業能接受的可靠度壽命。此外,在重新佈線層之設計方面,導線與墊片之連接角度,建議與主要熱膨脹係數不匹配方向平行,且此角度對應力的影響極為敏感;而U型彎曲結構可吸收導線和填充材料的膨脹,以減緩晶片墊片上的應力集中情形。此外,第一重新佈線層上的熱機械行為並不隨導線與墊片之連接角度和U型彎曲結構而有所改變,但使用較硬的導線保護層材料可減少第一重新佈線層的變形,進而減緩晶片墊片的應力集中現象。 模擬設計法(design-on-simulation)對於電子封裝產業發展新型封裝結構有其必要性。未來微電子封裝之整體設計、熱分析和結構可靠度評估可藉由此數值方法搭配適當的實驗驗證,來進行研發與設計。此分析流程可有效的減少新興電子產品的上市時程與製造成本。

並列摘要


Recently, physical limitations restrict the development of microelectronic industry following Moore’s law. To achieve high performance, small form factor and lightweight application, the electronic packaging has developed following more than Moore’s law which is fulfilled by system-in-package (SiP) or 3D packaging approaches. This research proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. It can resolve the problem of assembling fine-pitched chip to coarse-pitched PCB through redistribution layer (RDL). The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. The thermal performance of the WLCSP is compared with the proposed structure. It indicates that the thermal resistance is reduced from 49 °C/W to 39 °C/W, because the proposed packaging structure has a larger size silicon carrier to improve the capability of heat dissipation. According to the thermo-mechanical behavior of the double-sided with double-chip stacking structure during thermal cycling loading, the overall reliability assessment for solder joints and RDLs through FE analysis are studied. The application of soft lamination material and the selection of carrier material whose CTE is close to that of PCB can effectively enhance the reliability of solder joints more than 1,000 cycles. Base on the proposed design guideline, the large dies and NAND stacked flash dies are successfully applied on the proposed structure, and the life time predicted in this research is accepted by most electronic packaging industries. Besides, the double-side capability is applied on the proposed structure; the first and second RDLs are established in FE model. The strain values of the first RDL are not varied along with changing of trace layout. Stiff passivation material can prevent the deformation of the first RDL caused by out-of-plane movement to diminish the equivalent plastic strain at copper via. For the second RDL, the direction of the trace/pad junction which is parallel to the major direction of the CTE mismatch is recommended. The curved portion can absorb the expansion of metal line and filler material, and the stress concentration happens at via is reduced. The design-on-simulation (DOS) methodology is necessary in developing novel packaging structure in the electronic packaging industry. The overall design, thermal analysis, and structural reliability assessment for future microelectronic packaging can be analyzed through numerical method with suitable validation. The analytic procedure can effectively reduce time-to-market and fabrication cost of new electronic devices.

參考文獻


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