應用在基於QEMU的多核心系統平行模擬器的分離式二進制程式碼快取模型

A Separate Code Cache Model for a Parallel Multi-Core System Emulator Based on QEMU

簡嘉宏(Chia-Hung Chien)

指導教授 ： 鍾葉青

國立清華大學/電機資訊學院/資訊工程學系/碩士(2010年)

https://doi.org/10.6843/NTHU.2010.00476

摘要

QEMU 是一個應用動態二進制轉譯技術來達到高效模擬的高速處理器模擬器。我們可以應用QEMU，在某個指令集架構的機器上跑為另一個指令集架構設計的各種操作系統和程式。儘管如此，現階段QEMU的設計只適合單核心處理器的模擬。當在多核心機器上執行多執行緒的應用程式時，QEMU只能用循序執行的方式模擬，不能善用多執行緒平行運算的特性以及底層的架構。本論文提出新穎的多執行緒QEMU設計，又名P-QEMU 。它可以在底層多核心機器的架構下，有效地運用多顆虛擬處理器。本設計主要的想法是在QEMU 執行流程中，加入分離式二進制程式碼快取模型。為了評估這項設計，我們在四核心x86 i7的系統上用P-QEMU來模擬ARM11 MPCore的機器，並使用SPLASH-2，PARSEC，還有CoreMark當作實驗評估標準程式。SPLASH-2的實驗結果顯示，P-QEMU的效能平均上比QEMU快3.79倍，並且在四核心x86 i7的系統上，效能具有可擴展的特性。

關鍵字

二進制程式碼快取 ； 平行 ； 系統模擬器 ； 多核心 ； QEMU

並列摘要

QEMU is a fast processor emulator by adopting dynamic binary translation techniques to achieve high emulation efficiency. With QEMU, various operating systems and programs created for one ISA can be run on a machine with a different ISA. However, the current design of QEMU is only suitable for single-core processor emulation. When executing a multi-threaded application on a multi-core machine, QEMU emulates the execution of the application in serial and cannot take advantage of the parallelism available in the application and the underlying hardware. In this work, we propose a novel design of a multi-threaded QEMU, called P-QEMU, which can effectively deploy multiple simulated virtual CPUs on the underlying multi-core machine. The main idea of the design is to add a Separate Code Cache model to the execution flow of QEMU. To evaluate the design, we emulate an ARM11 MPCore by running P-QEMU on a quad-core x86 i7 system and use SPLASH-2, PARSEC, and CoreMark as benchmarks. The experimental results show that the performance of P-QEMU is, on average, 3.79 times faster than that of QEMU and is scalable on the quad-core i7 system for the SPLASH-2 benchmark suite.

並列關鍵字

Code Cache ； parallel ； system emulator ； Multi-core ； QEMU

參考文獻

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