考慮製程變異下在後矽根據診斷技術結果調整電壓之方法

A Post-Silicon Voltage-tuning Methodology for Process Variation based on Diagnosis Results

吳國立(Kuo-Li Wu)

指導教授 ： 劉靖家

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

當半導體的製程技術進入奈米等級後，製程變異 (Process varaition) 的影響越來越嚴重，導致晶片的良率持續地惡化。近年來，許多後矽調整技術廣泛的被運用，藉由增加功率消耗來補償失敗晶片的變異。在「1」論文中，作者提出了一套以列電壓調控為基礎的可調式電路設計機制 (row-based tunable design)，此機制允許使用者可以逐列地調整工作電壓 (supply voltag)。在可調整電路中，供給電壓(VDD)與接地電壓(GND)皆可以相較於正常電壓調整+/-0.2伏，也就是說每一個電壓都有三種值。所以在本篇論文中，我們提出了一套考慮製程變異下根據診斷技術結果來做電壓調整的機制，可增加部分電路的速度或是降低動態功率消耗。首先，由量測結果可得知失敗的晶片，再藉由論文「2」的診斷技術可得到晶片的時脈資訊。最後根據診斷的結果做VDD和GND電壓調整，讓修正過後的晶片符合我們所需的規格。
　　在實驗方面，本論文的電路採用180奈米製程技術。本實驗以調整整顆晶片電壓方法(Full-chip tuning)來做比對。在s38584中，我們的方法在加入不同的時脈延遲下動態消耗功率分佈在-3.07%到24.41%間，調整整顆晶片動態消耗功率分佈在0%到49.43%間，節省的動態功率可以達25%。在b17中，節省的動態功率可以達30%。由上實驗我們可以知道，越大的電路可以讓動態功率消耗節省越多、良率越高。本論文提出的演算法不僅可以有效地修正失敗的晶片且可以節省功率消耗。

關鍵字

製程變異 ； 可調式電路 ； 提升良率 ； 診斷

並列摘要

Process variation become increasingly serious as the semicondouctor technology keeps advancing
toward nanometer scales. Recently, several post silicon tuning techniques have been widely
used to compensate the variation of failing chips, though at the cost of increasing power consumption.
In [1],the authors proposed a row-based tunable design methodology which allows users to
fine-tune the supply voltages of manufactured chips. In this tunable circuits, the supply voltage
(VDD) and ground voltage (GND) can be adjusted up to +/- 0.2 Volt over the nominal voltage
respectively, e.g. the voltage level of each cell could have three possibilities. So we proposed a
post-silicon voltage tuning methodology for process variation based on diagnosis results by this
tunable circuit, which we can selectively tune up the voltages to increase the speed of parts of the
circuits or tune them down to save power. First, once a chip was found failure by delay testing.
Then we will use the diagnosis process [2] to get timing data of the chip. Finally, use voltage assignment
program [3] to adjust VDD and GND by row to fix the timing violation which is affected
by process variation.
In the experiments, we have applied our method on circuit under 180nm process node and
compare with the full chip tuning method. In s38584, the range of dynamic power overhead is
-3.07% to 24.41% compared to a typical voltage assignment case by our method. And the range
of dynamic power overhead is 0% to 49.43% compared to a typical voltage assignment case by
full-chip tuning. We can saving as high as 25% of dynamic power by our method. And in b17, we
can save as high as 25% of dynamic power by out method. The proposed algorithm can not only
effectively fix failed chip in timing but reduce the power consumption.

並列關鍵字

Process Variation ； Cell-based Tunable Circuit ； Increasing Yield ； diagnosis

參考文獻

[4] M. Choi and L. Milor, “Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing,” IEEE Transactions on Computer-Aided Design

of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1350–1367, 2006.

[5] M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf, “The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 4, pp. 360–368, 1997.

[6] K. Bowman, S. Duvall, and J. Meindl, “Impact of die-to die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE Journal of Solid-State Circuits, vol. 37, no. 2, pp. 183–190, 2002.

[7] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” ACM/IEEE Design Automation Conference, pp. 338–342, 2003.